SHA-256 (Secure Hash Algorithm 256-bit) hardware is implemented in Verilog and C and verifcated in SystemVerilog.

Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL

The MOD-10 counter was functionally verified using a Verilog testbench to validate reset, load, increment, and rollover operations. Out of 2987 executed test cases, 2937 passed successfully, achieving a verification accuracy of approximately 98.33%.

Parameterizable UART core with 8N1 format, configurable baud rates (1200–19200) and data width (6–8 bits). Features 16× oversampling, centre sampling, full status outputs (busy, ready, done), and a self‑checking testbench. Written in clean, synthesizable RTL.

An FPGA-accelerated High-Frequency Trading design on the Xilinx Zynq-7020 (PYNQ-Z2)

An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.

RTL code of an 8-bit CPU designed in Verilog.

AES-128 (Advanced Encryption Standard 128-bit) module written in Verilog for FPGA/ASIC use.

A high performance DMA subsystem using AXI4 Full protocols and a custom 16 bank eDRAM architecture. Designed for maximum throughput and minimal leakage, it features predictive bank wakeup logic and deterministic timing closure at 100MHz.

FPGA-based traffic light controller using VHDL, featuring FSM control, clock prescaling, testbench verification, and Basys 3 deployment

This project demonstrates a complete RTL-to-GDSII digital VLSI design flow. I designed a 4-bit Arithmetic Logic Unit (ALU) using Verilog HDL, verified its functionality through simulation, and implemented its physical layout on the SkyWater 130nm PDK using the OpenLane flow.

ALU (4 modes of operation)

This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7

A collection of 5 RTL digital design modules implemented in Verilog and simulated using ModelSim — covering UART, FIFO, Traffic Light Controller, Automatic Temperature Control, and Washing Machine Controller, each designed using FSM-based architecture with draw.io block diagrams, state transition tables, and waveform verification.