M.S. Electrical & Computer Engineering, UC Davis (2026)
Specializing in Design Verification, FPGA development and FPGA-based hardware acceleration.
I love building and verifying digital hardware systems: from RTL design to silicon-level validation, and from SoC acceleration to PCB design.
- Design Verification (SystemVerilog, UVM, assertion-based verification)
- FPGA Acceleration (Xilinx Zynq, Intel MAX10, PYNQ)
- Hardware-Software Co-design on SoCs
- Embedded ML acceleration
- PCB Design (Altium)
HDL: SystemVerilog · Verilog · VHDL
Verification: UVM · Assertions · Functional Coverage
FPGA Tools: Vivado · Quartus · PYNQ Framework
Languages: Python · C/C++
Hardware: Xilinx Zynq-7000 · Intel MAX10 · AXI4/DMA
- HFT on PYNQ-Z2 - ITCH 5.0 Decoder on Xilinx Zynq SoC
- DMA-Driven FIR Accelerator on PYNQ-Z2 — 4.77× speedup over SciPy via AXI-DMA + Xilinx FIR Compiler
- DE10-Lite RISC-V Core — 4-stage pipelined RV32I CPU on Intel MAX10 FPGA
- Coming soon!
Open to Design Verification and FPGA Engineer roles
See my work at: https://prnjl10.github.io/pranjals-portfolio/
Reach me on LinkedIn