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directed-testing

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abdo-ehab-euv / sram-controller-uvm-verification

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SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
  • Updated May 14, 2026
  • SystemVerilog

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