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pipelined-processor

Here are 16 public repositories matching this topic...

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic

Updated Oct 13, 2025
SystemVerilog

HafizMutahirAhmed / RV32I-5-Stage-Processor

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor

Updated Jul 27, 2025
SystemVerilog

yusronizza / riscv

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

open-source processor-architecture processor risc risc-v processor-design singlecycle-processor pipelined-processor

Updated Jan 7, 2025
Verilog

StackedArchitect / Fault-Tolerant-RISCV

A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor

Updated Jun 26, 2025
Verilog

EslamAsHhraf / Pipelined-Processor

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor

Updated Oct 16, 2023
Verilog

aGhandhii / pipelined-arm64-processor

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

arm64 systemverilog computer-architecture legv8-arm pipelined-processor

Updated Nov 12, 2023
SystemVerilog

pranav0x0112 / RISCape

RISCape is a 5-stage pipelined RISC-V processor

risc-v rv32i pipelined-processor

Updated Oct 12, 2025
SystemVerilog

algorhtym / mips-pipelined-processor

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

vhdl mips-architecture risc-processor structural-vhdl pipelined-processor

Updated Apr 11, 2023
VHDL

helcsnewsxd / armv8-pipelined-hazard-handling

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

python processor-architecture analysis assembly lab university-project forwarding computer-architecture hazard-detection system-verilog armv8 quartus hardware-description-language processor-design famaf pipelined-processor

Updated May 27, 2025
SystemVerilog

avnlk / MIPS_Processor

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

mips processor mips-processor pipelined-processor

Updated Mar 29, 2024
Python

RISC-Processor / Pipelined-Processor

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

risc-v processor-design pipelined-processor

Updated Apr 13, 2025
Verilog

StackedArchitect / MIPS32Bit-Pipelined-CPU

This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning about pipelined processor design and simulation.

cpu verilog vivado risc mips-architecture mips32 custom-processor pipelined-processor

Updated Jul 14, 2025
Verilog

vesalbargi / verilog-pipelined-cpu

A ModelSim project that implements a MIPS pipelined CPU in Verilog, enhancing efficiency through pipelining based on single-cycle CPU concepts.

mips verilog modelsim computer-architecture-lab pipelined-processor

Updated Sep 18, 2025
Verilog

mragetsars / RISC-V-Pipeline-Processor

the Register Transfer Level (RTL) implementation of a Pipelined RISC-V Processor . This project was developed as the Fourth Assignment for the Computer Architecture course at the University of Tehran.

verilog computer-architecture modelsim pipelined-processor

Updated Feb 6, 2026
Verilog

linukaratnayake / RV32I-Pipelined-Processor

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

risc-v processor-design pipelined-processor

Updated Apr 14, 2025
Verilog

InvincibleJuggernaut / SiPi

Design and Implementation of a 6-stage pipelined MIPS based processor

verilog mips-architecture forwarding-unit pipelined-processor hazard-detection-unit

Updated Aug 30, 2025
Verilog

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