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Merged
nathanaelhuffman merged 2 commits into from
Feb 9, 2026
Merged

Ndh/espi vis #461

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9af73f3
Remove an un-used I2CCore.rdl which was not used and had typos etc
nathanaelhuffman Feb 6, 2026
d68e394
Increase espi register visibility
nathanaelhuffman Feb 7, 2026
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25 changes: 0 additions & 25 deletions hdl/ip/bsv/I2C/BUCK
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Original file line number Diff line number Diff line change
@@ -1,30 +1,5 @@
load("//tools:bsv.bzl", "bsv_bluesim_tests")
load("//tools:bsv.bzl", "bsv_library")
load("//tools:rdl.bzl", "rdl_file")

# rdl_file
# Note: Buck2 RDL rule enforces strict naming convention
# BSV outputs use "Regs" suffix, VHDL uses "_pkg" suffix
rdl_file(
visibility = ["PUBLIC"],
name = "I2CCore_rdl",
outputs = [
"I2CCoreRegs.bsv",
"I2CCore.html",
"I2CCore.json",
],
src = "I2CCore.rdl",
)

# bsv_library
bsv_library(
visibility = ["PUBLIC"],
name = "I2CCoreRegs",
srcs = [":I2CCore_rdl"],
deps = [
"//hdl/ip/bsv:RegCommon",
],
)

# bsv_library
bsv_library(
Expand Down
72 changes: 0 additions & 72 deletions hdl/ip/bsv/I2C/I2CCore.rdl
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This file was deleted.

1 change: 1 addition & 0 deletions hdl/ip/vhd/espi/BUCK
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Expand Up @@ -18,6 +18,7 @@ rdl_file(
rdl_file(
name = "espi_regs_rdl",
src = "sys_regs/espi_regs.rdl",
deps = [":espi_spec_regs_rdl"],
outputs = ["espi_regs_pkg.vhd", "espi_regs.html", "espi_regs.json"],
visibility = ['PUBLIC']
)
Expand Down
14 changes: 14 additions & 0 deletions hdl/ip/vhd/espi/espi_spec_regs.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use work.espi_spec_regs_pkg.all;
use work.espi_spec_regs_view_pkg.all;
use work.link_layer_pkg.all;
use work.espi_base_types_pkg.all;

Expand All @@ -26,6 +27,9 @@ entity espi_spec_regs is
regs_if : view regs_side;
espi_reset : in std_logic;

-- Read-only view of all spec registers for the sys_regs block
spec_regs_view : view spec_regs_source;

qspi_mode : out qspi_mode_t;
wait_states : out std_logic_vector(3 downto 0);
oob_enabled : out std_logic;
Expand All @@ -41,6 +45,7 @@ architecture rtl of espi_spec_regs is
signal ch1_capabilities : ch1_capabilities_type;
signal ch2_capabilities : ch2_capabilities_type;
signal ch3_capabilities : ch3_capabilities_type;
constant ch3_capabilities2 : ch3_capabilities2_type := rec_reset;
signal readdata_valid : std_logic;
signal readdata : std_logic_vector(31 downto 0);
signal qspi_freq : qspi_freq_t;
Expand All @@ -53,6 +58,15 @@ begin

flash_channel_enable <= ch3_capabilities.flash_channel_enable = '1';
oob_enabled <= ch2_capabilities.chan_en;

spec_regs_view.device_id <= device_id;
spec_regs_view.general_capabilities <= gen_capabilities;
spec_regs_view.ch0_capabilities <= ch0_capabilities;
spec_regs_view.ch1_capabilities <= ch1_capabilities;
spec_regs_view.ch2_capabilities <= ch2_capabilities;
spec_regs_view.ch3_capabilities <= ch3_capabilities;
spec_regs_view.ch3_capabilities2 <= ch3_capabilities2;

-- Write-side of the spec-defined registers
write_reg: process(clk, reset)
begin
Expand Down
22 changes: 19 additions & 3 deletions hdl/ip/vhd/espi/espi_target_top.vhd
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Expand Up @@ -14,6 +14,7 @@ use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use work.qspi_link_layer_pkg.all;
use work.espi_base_types_pkg.all;
use work.espi_spec_regs_view_pkg.all;
use work.flash_channel_pkg.all;
use work.uart_channel_pkg.all;
use work.link_layer_pkg.all;
Expand Down Expand Up @@ -68,6 +69,7 @@ architecture rtl of espi_target_top is
signal flash_c_avail : std_logic;
signal flash_channel_enable : boolean;
signal dbg_chan : dbg_chan_t;
signal spec_regs : spec_regs_t;
signal response_done : boolean;
signal pc_free : std_logic;
signal pc_avail : std_logic;
Expand Down Expand Up @@ -107,6 +109,10 @@ architecture rtl of espi_target_top is
signal oob_enabled : std_logic;
signal stuff_fifo : std_logic;
signal stuff_wds : std_logic_vector(15 downto 0);
signal last_resp_status : std_logic_vector(15 downto 0);
signal host_to_sp_fifo_usedwds : std_logic_vector(12 downto 0);
signal oob_free_saw_full : std_logic;
signal live_espi_status : std_logic_vector(15 downto 0);

begin

Expand Down Expand Up @@ -254,11 +260,16 @@ begin
stuff_fifo => stuff_fifo,
stuff_wds => stuff_wds,
dbg_chan => dbg_chan,
spec_regs_view => spec_regs,
post_code => post_code,
post_code_valid => post_code_valid,
espi_reset => espi_reset_strobe_syncd,
to_host_tx_fifo_usedwds => to_host_tx_fifo_usedwds,
ipcc_to_host_byte_cntr => ipcc_to_host_byte_cntr
ipcc_to_host_byte_cntr => ipcc_to_host_byte_cntr,
live_espi_status => live_espi_status,
last_resp_status => last_resp_status,
host_to_sp_fifo_usedwds => host_to_sp_fifo_usedwds,
oob_free_saw_full => oob_free_saw_full
);

-- txn layer blocks
Expand Down Expand Up @@ -292,7 +303,9 @@ begin
np_avail => np_avail,
oob_free => oob_free,
oob_avail => oob_avail,
vwire_avail => vwire_avail
vwire_avail => vwire_avail,
live_espi_status => live_espi_status,
last_resp_status => last_resp_status
);

-- espi-internal register block
Expand All @@ -302,6 +315,7 @@ begin
reset => reset,
espi_reset => espi_reset_strobe_syncd,
regs_if => regs_if,
spec_regs_view => spec_regs,
qspi_mode => qspi_mode,
wait_states => wait_states_slow,
flash_channel_enable => flash_channel_enable,
Expand Down Expand Up @@ -350,7 +364,9 @@ begin
oob_avail => oob_avail,
oob_free => oob_free,
to_host_tx_fifo_usedwds => to_host_tx_fifo_usedwds,
ipcc_to_host_byte_cntr => ipcc_to_host_byte_cntr
ipcc_to_host_byte_cntr => ipcc_to_host_byte_cntr,
host_to_sp_fifo_usedwds => host_to_sp_fifo_usedwds,
oob_free_saw_full => oob_free_saw_full
);

-- vwire channel logic
Expand Down
18 changes: 18 additions & 0 deletions hdl/ip/vhd/espi/peripheral_channel/uart_channel_top.vhd
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Expand Up @@ -55,6 +55,9 @@ entity uart_channel_top is
np_avail: out std_logic;
to_host_tx_fifo_usedwds : out std_logic_vector(log2ceil(fifo_depth) downto 0);
ipcc_to_host_byte_cntr : out std_logic_vector(31 downto 0);
host_to_sp_fifo_usedwds : out std_logic_vector(log2ceil(fifo_depth) downto 0);
-- Sticky: set when oob_free goes low, cleared only by espi_reset
oob_free_saw_full : out std_logic
);

end entity;
Expand Down Expand Up @@ -84,6 +87,7 @@ architecture rtl of uart_channel_top is
begin

to_host_tx_fifo_usedwds <= tx_rusedwds;
host_to_sp_fifo_usedwds <= rx_wusedwds;

-- Not going to support any Non-posted transactions
-- on this interface
Expand Down Expand Up @@ -209,6 +213,20 @@ begin
end if;
end process;

-- Sticky detector: captures if oob_free ever went low since last espi_reset
oob_free_sticky: process(clk, reset)
begin
if reset then
oob_free_saw_full <= '0';
elsif rising_edge(clk) then
if espi_reset then
oob_free_saw_full <= '0';
elsif oob_free = '0' and enabled = '1' then
oob_free_saw_full <= '1';
end if;
end if;
end process;

from_host_rx_fifo: entity work.dcfifo_xpm
generic map(
fifo_write_depth => fifo_depth,
Expand Down
30 changes: 15 additions & 15 deletions hdl/ip/vhd/espi/sims/espi_tb.vhd
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Expand Up @@ -18,10 +18,10 @@ use work.qspi_vc_pkg.all;
use work.espi_controller_vc_pkg.all;
use work.espi_base_types_pkg.all;
use work.espi_spec_regs_pkg.all;
use work.espi_regs_pkg;
use work.espi_dbg_vc_pkg.all;
use work.espi_tb_pkg.all;

use work.espi_regs_pkg.all;
entity espi_tb is
generic (

Expand Down Expand Up @@ -105,15 +105,15 @@ begin
check_equal(response.status, expected_status, "Status did not match reset value");
exp_data_32 := (others => '0');
-- Should have an empty response queue
read_bus(net, bus_handle, To_StdLogicVector(STATUS_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.STATUS_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Response queue not empty before bad crc command");

-- Issue a command with a bad CRC
dbg_send_get_status_cmd(net, bad_crc => true);
dbg_wait_for_done(net);
wait for 1 us;
-- Expect no responses
read_bus(net, bus_handle, To_StdLogicVector(FIFO_STATUS_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.FIFO_STATUS_OFFSET, bus_handle.p_address_length), data_32);
exp_data_32 := (others => '0');
check_equal(data_32, exp_data_32, "Expected no response to bad CRC command");

Expand Down Expand Up @@ -250,19 +250,19 @@ begin
-- verify counts are correct.
wait for 1 us;
-- Check *last* post code register
read_bus(net, bus_handle, To_StdLogicVector(LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Single post code register readback failed");
-- Check post code buffer entry 0
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Post code buffer readback failed");
-- Check post code count register
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"00000001"), "Post code count register readback failed");

-- issue an espi reset and verify post code count resets
dbg_espi_reset(net);
wait for 1 us;
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"00000000"), "Post code count register did not reset after espi reset");


Expand All @@ -277,13 +277,13 @@ begin
dbg_wait_for_done(net);
wait for 1 us;
-- Check *last* post code register
read_bus(net, bus_handle, To_StdLogicVector(LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Single post code register readback failed");
-- Check post code buffer entry 0
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Post code buffer readback failed");
-- Check post code count register
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"00000001"), "Post code count register readback failed");

exp_data_32 := x"000101de";
Expand All @@ -293,21 +293,21 @@ begin
wait for 1 us;

-- Check *last* post code register
read_bus(net, bus_handle, To_StdLogicVector(LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.LAST_POST_CODE_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Single post code register readback failed");
-- Check post code buffer entry 0
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_BUFFER_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"000001de"), "Post code buffer 0 readback failed");
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_BUFFER_OFFSET + 4, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_BUFFER_OFFSET + 4, bus_handle.p_address_length), data_32);
check_equal(data_32, exp_data_32, "Post code buffer 1 readback failed");
-- Check post code count register
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"00000002"), "Post code count register readback failed");

-- issue an espi reset and verify post code count resets
dbg_espi_reset(net);
wait for 1 us;
read_bus(net, bus_handle, To_StdLogicVector(POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
read_bus(net, bus_handle, To_StdLogicVector(espi_regs_pkg.POST_CODE_COUNT_OFFSET, bus_handle.p_address_length), data_32);
check_equal(data_32, std_logic_vector'(x"00000000"), "Post code count register did not reset after espi reset");

elsif run("put_iowr_short") then
Expand Down
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