[sw] BootROM default is SPI bootstrap#625
Conversation
This is a better default because on FPGA the LEDs will show activity when the bitstream is first flashed and both DRAM and SRAM are disabled. Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
marnovandermaas
force-pushed
the
bootrom_default
branch
from
33b91d6 to
f1e29cf
Compare
| timer_init(boot_ctx.timer); | ||
| timer_enable_write(boot_ctx.timer, true); | ||
| if (bootstrap_requested(&boot_ctx)) { | ||
| if (bootstrap_requested(&boot_ctx) || !get_boot_addr(&boot_addr)) { |
There was a problem hiding this comment.
This will break the opensbi flow in simulation because it doesn't have the magic number. We need to figure out a better solution.
There was a problem hiding this comment.
what if we flash the LEDs inside the exception handler?
There was a problem hiding this comment.
Yes, I agree that is a better solution!
|
I'm sorry for accidentally closing the PR. |
|
Converted to draft as is breaks the OpenSBI flow on Verilator. @engdoreis is working on a better solution in the meantime. |
|
I'm not sure about this. The rationale for boot ROM defaulting to jumping straight to DRAM was to not need any host-side software to bypass Bootstrap mode in Verilator simulation - where binaries are loaded by backdoor instead. We also cannot test the presence of a magic number because the magic number is optional in case the next boot address should be different - e.g jumping into SRAM instead of the default DRAM, and this boot magic mechanism and SRAM tests is planned to be removed when #615 is merged (issue #514). |
|
Closing in favour of github.com//pull/630 |
3 participants
This is a better default because on FPGA the LEDs will show activity when the bitstream is first flashed and both DRAM and SRAM are disabled.
Closes: #624