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I forgot that the core files are autogenerated :(( Failing lint |
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martin-velay
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I have some initial comments. It's a very good start though!
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HI @martin, Thanks for the detailed review. I realized yesterday that the comments I added in the test and vseq were way more difficult and I spent some time making it a bit easier to understanding. Do you mind take another look? Some of your comments are unresolved because either I asked for a go-ahead or a question in replies. |
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The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO test for Xcelium. That test fails on verilator. The reason being different tops used for both of the tools. For Xcelium, an interface is connecting the UVM to the GPIO. The UVM have the control to drive GPIOs inputs. In lowRISC#382, the SW waits for a specific pattern driven by UVM to appear in `data_in` reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive the inputs depends on a host SW infrastructure which is currently missing. With the above context, the best way forward is to separate the GPIO smoketest for both of the simulators for now to make the CI happy. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO test for Xcelium. That test fails on verilator. The reason being different tops used for both of the tools. For Xcelium, an interface is connecting the UVM to the GPIO. The UVM have the control to drive GPIOs inputs. In lowRISC#382, the SW waits for a specific pattern driven by UVM to appear in `data_in` reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive the inputs depends on a host SW infrastructure which is currently missing. With the above context, the best way forward is to separate the GPIO smoketest for both of the simulators for now to make the CI happy. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO test for Xcelium. That test fails on verilator. The reason being different tops used for both of the tools. For Xcelium, an interface is connecting the UVM to the GPIO. The UVM have the control to drive GPIOs inputs. In lowRISC#382, the SW waits for a specific pattern driven by UVM to appear in `data_in` reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive the inputs depends on a host SW infrastructure which is currently missing. With the above context, the best way forward is to separate the GPIO smoketest for both of the simulators for now to make the CI happy. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms ( DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In lowRISC#382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible paltforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Reason being that lowRISC#382 is adding another test which will check if every outputs and inputs can be driven in high/low combinations. That is a much refined definition of a smoke test. The second reason of renaming gpio/smoketest.c to gpio/reg_access_test.c is that the test added in the PR lowRISC#382 is incompatible for Verilator and FPGA tops. This also requires to ask the build system to only make images of GPIO tests for their compatible tops. So, the better approach is to rename the test after their features and add additional options to the build system in order to make their images for different platforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Reason being that #382 is adding another test which will check if every outputs and inputs can be driven in high/low combinations. That is a much refined definition of a smoke test. The second reason of renaming gpio/smoketest.c to gpio/reg_access_test.c is that the test added in the PR #382 is incompatible for Verilator and FPGA tops. This also requires to ask the build system to only make images of GPIO tests for their compatible tops. So, the better approach is to rename the test after their features and add additional options to the build system in order to make their images for different platforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms ( DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In lowRISC#382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible paltforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms ( DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In lowRISC#382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible paltforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms ( DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In lowRISC#382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exact test with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible paltforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from lowRISC#382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms (DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In 382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exacttest with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible plaforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
The motivation of this PR comes from #382 which is adding a chip level GPIO smoke test. That test fails on verilator. Reason being different tops used for different platforms (DVSim(Xcelium), Verilator, FPGA). For Xcelium, an interface is connecting the UVM to the GPIO. UVM has the control to drive GPIOs inputs. In 382, SW waits for a specific pattern driven by UVM to arrive in data_in reg. If we run the exacttest with the verilator top, which is using GPIO DPI, then the abilty to drive inputs depends on a host SW infrastructure which is currently missing. Second problem is that we use cmake to build software images for DVSim, verilator and FPGA. We run tests on FPGA and Verilator in CI. If the build system develops an Xcelium compatible image and feed that image to Verilator and FPGA to execute the test in CI then the test will fail due to the reason given in the first paragraph. Hence, the best way forward is to make images only for the compatible plaforms. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
This test is supposed to work in pair with UVM and FPGA. Through UVM, we intend to drive the inputs but we can't yet achieve this functionality through verilator and FPGA tops. Thus, ask the build system to skip making verilator and FPGA images to run that test and this is only compatible for a DVSim top now. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Both SW and vseq works in pairs. The SW drives the pins in outputs and set each pin in walking 1's fashion and waits for the pattern driven by vseq. The vseq once seen all the W1's pattern on each pin will then drive a pattern on GPIO inputs and SW waits for that pattern by reading `data_in` reg. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
…le SW images Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
engdoreis
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The Software changes LGTM.
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Converting to draft as it depends on #442 |
| // Assignment to the GPIO pads. If dut_gpio_en_o[i] is disabled, then let the gpio_pad[i] float so | ||
| // an external device/driver can drive it. | ||
| for (genvar i = 0; i < NUM_GPIOS; i++) begin : gen_gpio_pads | ||
| assign gpio_pads[i] = dut_gpio_en_o[i] ? dut_gpio_o[i] : 1'bz; |
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I just bumped into this when trying to make the bootrom boostrap pin to work with dvsim. Is it possible to make the pin 8 high if output enable high rathen then floating?
Merge #442 as dependency
This PR added functionality to make the gpio smoketest working on the chip level.
Will close: #147