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Holy-Mahdi/README.md

Mahdi Mohammadi

Electrical Engineering Student

Verilog · MATLAB · Python · C++

☀️🦁

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  1. MIPS-Single-Cycle MIPS-Single-Cycle Public

    A modular 32-bit Single-Cycle MIPS processor implementation in Verilog.

    Verilog

  2. parametric-ALU parametric-ALU Public

    A flexible, N-bit Parametric Arithmetic Logic Unit (ALU) designed in VHDL

    VHDL

  3. sv-axi-sram-controller sv-axi-sram-controller Public

    A SystemVerilog implementation of an AXI4-Lite to SRAM controller.

    SystemVerilog

  4. SystemVerilog-RISC-V-Core SystemVerilog-RISC-V-Core Public

    A high-performance 5-stage pipelined RISC-V RV32I core implemented in SystemVerilog with full ISA compliance, hazard detection, and comprehensive verification.

    SystemVerilog