ODLY. Calibration fix

There was an intermittent problem with the handling of rwds which would cause the first word returned word from the hyperram memory to be dropped on reads.

Post merge results with phased clock solution branch

Post merge tag of hyperram controller with phased clock solution for HDIO pins without IDELAY/ODELAY resources.

Tag before merge of phased clock solution

This is a tag of the working IDELAY/ODELAY solution before merging with the phased clock solution

First Release of HyperBus controller for HyperRam devices

Recently I decided to experiment a bit with AI assisted FPGA design.

I wanted to use the HyperRam device that is present on AMD's recently released SCU35P Evaluation Board but I needed some IP to talk it. After spending some time to read the datasheet for a HyperRam device, I felt this would be a good medium level complexity project to try AI on.

This is part of my overall interest in experimenting with some ideas for a Spartan UltraScale+ based drone flight controller.

The results are quite amazing. Using ChatGPT-Codex, in a few days, I had running simulations with meaningful test coverage.

I spent the time afterwards focusing on changes needed to actually have a working design after Vivado implementation.

This design is verified working on a SCU35P Evaluation Board running for about 5 days continuously. It should also work for other UltraScale+ devices. I also added 7-Series FPGA support. Passing in simulation, but not verified in hardware yet.