Open source implementation of the blob running on the Cortex M0.
- PLL, very basic clocks
- UART
- Efuse
- DRAM init (tested on 32, 64 and 128 MB)
- USB
- Download protocol for stage 2
- NAND/NOR
- microSD (probably)
- Pinctrl, non-basic clocks
- stefand - lots of reverse engineering for this SoC; testing (64 MB)
- Mio-sha512 - DRAM & USB & protocol drivers; testing (32 MB)
- jschwartzenberg - testing (64MB)
- exp-3 - testing (32MB)