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Fix: error with slice when using descript_scheduler#27

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yadej wants to merge 9 commits intoxtc-tools:mainfrom
yadej:dev/rcesista/spec_schedule_bug
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Fix: error with slice when using descript_scheduler#27
yadej wants to merge 9 commits intoxtc-tools:mainfrom
yadej:dev/rcesista/spec_schedule_bug

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@yadej yadej commented Jan 27, 2026

Add a minimal failing example for descript_scheduler

Discussion of the error is in that issue #26

@guillon guillon added the enhancement New feature or request label Jan 28, 2026
@guillon guillon requested a review from qaco January 28, 2026 09:26
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qaco commented Jan 28, 2026

Cool ! Do you want to dig into the bug (probably in descript.py) and fix it in the same PR ? It could be a good exercise to discover XTC deeper. If you prefer, I can do it.

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yadej commented Jan 28, 2026

I want to try to fix it

@yadej yadej force-pushed the dev/rcesista/spec_schedule_bug branch from ebd6146 to 98b2aff Compare January 29, 2026 15:52
@yadej yadej changed the title Add test file for error with slice when using descript_scheduler Fix: error with slice when using descript_scheduler Jan 29, 2026
new_interchange = []
for loop_name in sched.interchange:
if not loop_name in sched.splits_to_sizes:
loop_name = re.sub(r"\[.*?\]$", "", loop_name)
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@qaco qaco Jan 30, 2026

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Here you recover the abstract axis from the split declaration using the naming convention, am I right ? Why is it not in splits_to_sizes ?

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When we create a inner_nest from the split the head of the interchange will be [i[0]] and [i[1]] for the 2 split and if we use splits_to_sizes on those slice there will be no i[0] or i[1] since it is only in the first splits_to_sizes slice

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@qaco qaco Feb 2, 2026

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Actually, you've put your finger on a misconception that I introduced (see my comment on my PR). Thank you !

In fact, I added these heads because in MLIR, the split cuts the linalg operator but doesn't materialize the loops, so this head corrects the behavior. But this should be handled at the MLIR backend level, not at the abstract/descript schedule level. At this point, I think we need to remove this head mechanism which is really error-prone.

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Now that part is done on mlir backend instead of descript

self._check_tiling_consistency()
self._check_sizes()

def remove_excess_interchange(self):
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If I understand well, the point here is to express "i, j[X], k" as "i, j, k" ?

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that's right

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Once they are created, we should not change the names, because they identify uniquely a loop. In this case, the problem is deeper : this loop should not exist (see my other comment).

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It is now removed

@yadej yadej force-pushed the dev/rcesista/spec_schedule_bug branch from 98b2aff to 3ab1ee6 Compare February 3, 2026 12:36
continue
loop_name_no_root = loop_name.rsplit("/", 1)[-1]
loop_name_no_root = loop_name_no_root.split("[")[0]
loop_name = root + "/" + loop_name_no_root
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Do I keep that to have the node name such as __node0__/J[0]/J or do I change it to __node0__/J[0]/J[0] but I will need to change most mlir splitting test

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No __node0__/J[0]/J is fine. But you need to build the name from the root + abstract axis, not from the split name (we want this algorithm to work even if name conventions change).

Besides could you please use ROOT_SEP instead of literal '/' ?

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I replaced the '/' with ROOT_SEP and put that in itf.schd.scheduler and added a constant SPLIT_LEFT_SEP for "[" and SPLIT_RIGHT_SEP for "]"

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I found a way to build the name with root and abstract axis without passing via string splitting

@yadej yadej requested a review from qaco February 3, 2026 12:51
f"Axis {axis_name} is scheduled twice (or more)."
)
for loop_name in interchange:
loop_name = re.sub(r"\[.*?\]$", "", loop_name)
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Same remark as above. We don't want to rely on naming conventions.


# Recursively interpret the nested schedule
inner_nest = self._interpret_spec(item.body, new_root_name, head=[axis_name])
inner_nest = self._interpret_spec(item.body, new_root_name, head=[new_dim_name])
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It seems to me that the parameter head is now useless. Do you agree ?

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Yes now the parameter head is removed

@yadej yadej force-pushed the dev/rcesista/spec_schedule_bug branch from 0120f52 to 97e5311 Compare February 20, 2026 10:28
@yadej yadej requested a review from qaco February 20, 2026 10:38
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3 participants