New computer and new CPU PoC

This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction scheduling.

A Python - Verilog combination that simulates the working of a 32-bit 5-stage pipelined VLIW processor from input assembly code while monitoring the updates in the processor register file.

Re-port of the OnDemand (RIP) Chili VLIW architecture to gcc-8.4 as a COVID-19 countermeassure

Balanced ternary logic SoC with CPU, memory controllers, and complete synthesis flow for silicon fabrication

Source code for the TM32 disassembler created by asbokid https://sourceforge.net/projects/tm32dis/

Anthropic Performance Take-Home: 1,339 cycles (110.3x speedup, 9/9 tests) — Claude Opus 4.6 solution

Revolutionary 18M transistor CPU outperforming Intel on parallel workloads through O(1) scheduling, bounded OoO, and zero-conflict architecture - $3.50/chip at 28nm vs Intel's $98

CS-470 Homework 2

Human-directed AI optimization loop on Anthropic's original performance take-home. 1,285 cycles, 114.97x speedup.