A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.
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Apr 19, 2026 - Verilog
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kria-kv260
Here are 20 public repositories matching this topic...
Automate the creation of a custom Ubuntu-based SD card image for the AMD/Xilinx Kria KV260 board using Docker
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Sep 15, 2025 - Shell
kria kv260 final project, Authors: L. P., K. P.
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Oct 11, 2025 - Jupyter Notebook
Unboxing and quick overview of AMD Kria KR260 Robotics Starter Kit
machine-learning computer-vision fpga deep-learning robotics hardware-acceleration opencv-python nomachine ros2-humble kria-kr260 kria-kv260
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Mar 26, 2026
Real-Time Object Detection on the Kria KR260 using a Webcam
machine-learning ai deep-learning object-detection opencv-python yolox kr260 ai-vision kria-kr260 kria-kv260
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Apr 3, 2026 - Python
A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.
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Mar 19, 2026 - Verilog
An AXI-native 8x8 systolic array accelerator in Verilog. Features pure dataflow pipelining, Q-format fixed-point arithmetic, and hardware validation on the Kria KV260 FPGA.
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Mar 19, 2026 - Verilog
Deterministic RTL RMS / Peak envelope detector for FPGA audio pipelines. AXI-Stream + AXI-Lite, fixed-point, cycle-accurate, real-time safe.
fpga verilog xilinx fixed-point rms audio-dsp peak-detection axi-stream iir-filter axi-lite envelope-detection kria-kv260
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Mar 23, 2026 - Verilog
RTL reference implementation of a QMF analysis/synthesis filter bank using AXI-Stream, focused on fixed-point DSP and hardware correctness.
fpga verilog xilinx fixed-point fir-filter audio-dsp axi-stream axi-lite quadrature-mirror-filter kria-kv260
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Mar 20, 2026 - Verilog
AXI4-Stream stereo audio delay implemented on FPGA, using BRAM-based circular buffers and AXI-Lite control.
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Mar 19, 2026 - Verilog
Getting started with ROS2 on AMD's Kria KR260 Robotics Starter Kit
machine-learning computer-vision robotics hardware-acceleration opencv-python dpu ros2-humble kr260 visionai kria-kr260 kria-kv260
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Apr 10, 2026 - Shell
Reference RTL implementation of a fixed-point IIR biquad filter with AXI-Stream and AXI-Lite control, validated on FPGA hardware.
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Mar 19, 2026 - Verilog
ROS 2 node for controlling MD80 actuators and publishing their states. Designed for use on embedded controllers (Kria/ARM64) as part of the BERNARD bipedal robot.
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Jan 8, 2026 - C++
Reference RTL implementation of a stereo gain stage, showcasing fixed-point DSP decisions and AXI integration on FPGA.
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Mar 22, 2026 - Verilog
Mid-Side transform RTL (encoder/decoder) in Verilog with AXI-Stream and AXI-Lite control, verified via cycle-accurate simulation on KV260.
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Mar 19, 2026 - Verilog
A first-order IIR filter for 16-bit PCM stereo data implemented on an FPGA with fixed-point representation.
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Mar 22, 2026 - Verilog
A practical comparision demonstrating: RT-IoT-2022 usage for binary (malicious or benign) and multi-class classification, ML (ensemble-based) and DL (CNN-based) models for training and comparison, and deployment trade-offs at the edge on an FPGA-equipped device - Kria KV260
iot machine-learning ai deep-learning random-forest edge xgboost cnn-classification cnn-attention fpga-acceleration vitis-ai kria-kv260
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Mar 26, 2026 - Jupyter Notebook
🎶 Implement a stereo FIR filter in Verilog with AXI-Stream for real-time audio processing, featuring configurable taps and deterministic latency.
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May 2, 2026 - SystemVerilog
🔊 Implement mid-side audio transforms on FPGA with this efficient Verilog module, focusing on real-time processing and fixed-point DSP integration.
fpga verilog xilinx fixed-point audio-dsp axi-stream github-config axi-lite mid-side-encoder mid-side kria-kv260
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May 2, 2026 - SystemVerilog
🔊 Implement and scale audio gain in real-time using a fixed-point DSP module on FPGA with AXI-Stream and AXI-Lite interfaces, designed for the AMD Kria KV260.
python music swift playground ios spider module tvos midi verilog xilinx gpt axi-stream axi-lite kria-kv260
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May 2, 2026 - SystemVerilog
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