Logic circuit analysis and optimization
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Updated
Feb 2, 2026 - Rust
Logic circuit analysis and optimization
A Web-based tool that helps analyze the correctness and equivalence of programs using formal methods.
Context-verified, error-budget-aware decomposition selection for Toffoli networks. Companion code to arXiv:2606.31791 (Bartkiewicz & Tulewicz, submitted to Quantum).
Lean formalization of how behavioral equivalence checking can be generalized through abstract intrepretation
Combinational logic equivalence check: two gate-level netlists in, an equivalence verdict (with counter-example) out.
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