32-bit Superscalar RISC-V CPU
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Updated
Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
Over-engineered SDR development board
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
My experiments with Nexys4 DDR Artix-7 FPGA Board
Complete end-to-end FPGA trading system: hardware acceleration (<5μs latency), kernel bypass (AF_XDP), automated market maker, FIX 4.2 execution engine. 30 projects from Ethernet PHY to multi-platform apps. Real NASDAQ ITCH validation (563K+ samples). Production-ready low-latency architecture.
Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
Alchitry Au FPGA Board Example Project
A tetris-game on screen using verilog.
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