boards: ace30: enable KCPS dynamic clock control

[abonislawski]

Enable dynamic clock switching for ACE30

[Copilot]

Pull Request Overview

This PR enables KCPS (Kilo Cycles Per Second) dynamic clock control for the Intel ADSP ACE30 PTL board configuration, allowing the system to dynamically adjust clock speeds at runtime.

Key Changes:

• Modified the ACE30 PTL board configuration to enable dynamic clock switching

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[lgirdwood]

@abonislawski I assume default is max clock if any CPC in missing ?

[abonislawski]

Yes, nothing has changed in this regard. I think we have most of the CPCs for PTL (but probably not all).

[lgirdwood]

A lot of red on the PTL SDW CI, rerun CI again in case its a DUT issue.

[lgirdwood]

SOFCI TEST

[lgirdwood]

@abonislawski there is an IPC timeout, see https://sof-ci.01.org/sofpr/PR10368/build17444/devicetest/index.html?model=PTLP_RVP_SDW&testcase=check-playback-3rounds

Could we have a wrong CPC somewhere ?

[abonislawski]

In the logs I can see we are switching clock 0->1->0 so looks like it is just unstable

[lgirdwood]

In the logs I can see we are switching clock 0->1->0 so looks like it is just unstable

More delay needed between clock changes ?

[tmleman]

@abonislawski any update?

[abonislawski]

Unstable in tests, waiting for debug. I will rebase to recheck