bonw16

src/include/cpu/intel/cpu_ids.h

@@ -86,6 +86,8 @@
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
 #define CPUID_LUNARLAKE_A0_2		0xb06d1
 #define CPUID_ARROWLAKE_H_A0		0xc0652
+#define CPUID_ARROWLAKE_S_A0		0xc0660
+#define CPUID_ARROWLAKE_S_B0		0xc0662
 #define CPUID_PANTHERLAKE		0xc06c0
 #define CPUID_SNOWRIDGE_A0		0x80660
 #define CPUID_SNOWRIDGE_A1		0x80661

src/include/device/pci_ids.h

@@ -4527,6 +4527,7 @@
 #define PCI_DID_INTEL_MTL_P_GT2_5			0x7dd5
 #define PCI_DID_INTEL_ARL_H_GT2_1			0x7d51
 #define PCI_DID_INTEL_ARL_H_GT2_2			0x7dd1
+#define PCI_DID_INTEL_ARL_HX_GT2			0x7d67
 #define PCI_DID_INTEL_RPL_HX_GT1			0xa788
 #define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
 #define PCI_DID_INTEL_RPL_HX_GT3			0x4688
@@ -4689,6 +4690,9 @@
 #define PCI_DID_INTEL_MTL_P_ID_5		0x7d16
 #define PCI_DID_INTEL_ARL_H_ID_1		0x7d06
 #define PCI_DID_INTEL_ARL_H_ID_2		0x7d20
+#define PCI_DID_INTEL_ARL_HX_ID_1		0x7d1c
+#define PCI_DID_INTEL_ARL_HX_ID_2		0x7d2d
+#define PCI_DID_INTEL_ARL_HX_ID_3		0x7d2f
 #define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
 #define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
 #define PCI_DID_INTEL_RPL_HX_ID_3		0xa728

src/mainboard/system76/mtl/Kconfig

@@ -26,6 +26,16 @@ config BOARD_SYSTEM76_MTL_COMMON
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_SYSTEM76_BONW16
+	select BOARD_SYSTEM76_MTL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_INTEL_DTBT
+	select EC_SYSTEM76_EC_DGPU
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_METEORLAKE_U_H # TODO: Arrow Lake-HX
+	select SOC_INTEL_ARROWLAKE_PCH_S
+
 config BOARD_SYSTEM76_DARP10
 	select BOARD_SYSTEM76_MTL_COMMON
 	select EC_SYSTEM76_EC_FAN2
@@ -74,6 +84,7 @@ config MAINBOARD_DIR
 	default "system76/mtl"
 
 config VARIANT_DIR
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
@@ -82,6 +93,7 @@ config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11
@@ -90,10 +102,12 @@ config MAINBOARD_PART_NUMBER
 	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Bonobo WS" if BOARD_SYSTEM76_BONW16
 	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B || BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
 
 config MAINBOARD_VERSION
+	default "bonw16" if BOARD_SYSTEM76_BONW16
 	default "darp10" if BOARD_SYSTEM76_DARP10
 	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
 	default "darp11" if BOARD_SYSTEM76_DARP11

src/mainboard/system76/mtl/Kconfig.name

@@ -1,5 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+config BOARD_SYSTEM76_BONW16
+	bool "bonw16"
+
 config BOARD_SYSTEM76_DARP10
 	bool "darp10"
 

src/mainboard/system76/mtl/variants/bonw16/board.fmd

@@ -0,0 +1,12 @@
+FLASH 32M {
+	SI_DESC 16K
+	SI_ME 10472K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/mtl/variants/bonw16/board_info.txt

@@ -0,0 +1,2 @@
+Board name: bonw16
+Release year: 2025

src/mainboard/system76/mtl/variants/bonw16/gpio.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+//TODO
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/mtl/variants/bonw16/gpio_early.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+//TODO
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/mtl/variants/bonw16/hda_verb.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15585802, /* Subsystem ID */
+	13, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585802),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60120),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41a7932d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/mtl/variants/bonw16/overridetree.cb

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/meteorlake
+	device domain 0 on
+		subsystemid 0x1558 0x5802 inherit
+
+		# TODO
+    end
+end

src/mainboard/system76/mtl/variants/bonw16/ramstage.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	//TODO: TCP USB-A conversion?
+
+	// XXX: Enabling C10 reporting causes system to constantly enter and
+	// exit opportunistic suspend when idle.
+	params->PchEspiHostC10ReportEnable = 0;
+}

src/mainboard/system76/mtl/variants/bonw16/romstage.c

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.ect = true,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x51
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x53,
+			},
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/soc/intel/common/block/cpu/mp_init.c

@@ -42,6 +42,8 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_A0, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_ARROWLAKE_S_B0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK },

src/soc/intel/common/block/graphics/graphics.c

@@ -392,6 +392,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_P_GT2_5,
 	PCI_DID_INTEL_ARL_H_GT2_1,
 	PCI_DID_INTEL_ARL_H_GT2_2,
+	PCI_DID_INTEL_ARL_HX_GT2,
 	PCI_DID_INTEL_APL_IGD_HD_505,
 	PCI_DID_INTEL_APL_IGD_HD_500,
 	PCI_DID_INTEL_CNL_GT2_ULX_1,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -456,6 +456,9 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_MTL_P_ID_5,
 	PCI_DID_INTEL_ARL_H_ID_1,
 	PCI_DID_INTEL_ARL_H_ID_2,
+	PCI_DID_INTEL_ARL_HX_ID_1,
+	PCI_DID_INTEL_ARL_HX_ID_2,
+	PCI_DID_INTEL_ARL_HX_ID_3,
 	PCI_DID_INTEL_GLK_NB,
 	PCI_DID_INTEL_APL_NB,
 	PCI_DID_INTEL_CNL_ID_U,

src/soc/intel/meteorlake/Kconfig

@@ -71,7 +71,7 @@ config SOC_INTEL_METEORLAKE
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_HDA
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
-	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ARROWLAKE_PCH_S
 	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
 	select SOC_INTEL_COMMON_BLOCK_IRQ
 	select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18
@@ -150,6 +150,11 @@ config SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
 	  silicon. Typically known as engineering samples (like ES). This type
 	  of the silicon are very common for early platform development.
 
+config SOC_INTEL_ARROWLAKE_PCH_S
+	bool
+	help
+	  Choose this option if your mainboard has an Arrow Lake PCH-S chipset.
+
 if SOC_INTEL_METEORLAKE
 
 config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT
@@ -171,7 +176,7 @@ config METEORLAKE_CAR_ENHANCED_NEM
 
 config MAX_CPUS
 	int
-	default 22
+	default 24
 
 config DCACHE_RAM_BASE
 	default 0xfef00000
@@ -201,6 +206,7 @@ config FSP_TEMP_RAM_SIZE
 
 config CHIPSET_DEVICETREE
 	string
+	default "soc/intel/meteorlake/chipset_pch_s.cb" if SOC_INTEL_ARROWLAKE_PCH_S
 	default "soc/intel/meteorlake/chipset.cb"
 
 config EXT_BIOS_WIN_BASE
@@ -239,14 +245,17 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config MAX_TBT_ROOT_PORTS
 	int
+	default 2 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 4
 
 config MAX_ROOT_PORTS
 	int
+	default 24 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 12
 
 config MAX_PCIE_CLOCK_SRC
 	int
+	default 14 if SOC_INTEL_ARROWLAKE_PCH_S
 	default 9
 
 config SMM_TSEG_SIZE

src/soc/intel/meteorlake/bootblock/report_platform.c

@@ -23,6 +23,8 @@ static struct {
 	{ CPUID_METEORLAKE_B0,   "MeteorLake B0" },
 	{ CPUID_METEORLAKE_C0,   "MeteorLake C0" },
 	{ CPUID_ARROWLAKE_H_A0,   "ArrowLake-H A0" },
+	{ CPUID_ARROWLAKE_S_A0,   "ArrowLake-S A0" },
+	{ CPUID_ARROWLAKE_S_B0,   "ArrowLake-S B0" },
 };
 
 static struct {
@@ -37,6 +39,9 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" },
 	{ PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" },
 	{ PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" },
+	{ PCI_DID_INTEL_ARL_HX_ID_1, "ArrowLake-HX (8+16)" },
+	{ PCI_DID_INTEL_ARL_HX_ID_2, "ArrowLake-HX (8+12)" },
+	{ PCI_DID_INTEL_ARL_HX_ID_3, "ArrowLake-HX (6+8)" },
 };
 
 static struct {
@@ -54,6 +59,38 @@ static struct {
 	{ PCI_DID_INTEL_ARL_H_ESPI_0, "ArrowLake-H SOC" },
 	{ PCI_DID_INTEL_ARL_H_ESPI_1, "ArrowLake-H SOC" },
 	{ PCI_DID_INTEL_ARL_U_ESPI_0, "ArrowLake-U SOC" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_0, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_1, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_2, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_3, "ArrowLake-S Q870" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_4, "ArrowLake-S Z890" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_5, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_6, "ArrowLake-S B860" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_7, "ArrowLake-S H810" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_8, "ArrowLake-S W880" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_9, "ArrowLake-S W890" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_10, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_11, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_12, "ArrowLake-S HM870" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_13, "ArrowLake-S WM880" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_14, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_15, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_16, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_17, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_18, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_19, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_20, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_21, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_22, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_23, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_24, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_25, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_26, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_27, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_28, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_29, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_30, "ArrowLake-S PCH" },
+	{ PCI_DID_INTEL_ARP_S_ESPI_31, "ArrowLake-S PCH" },
 };
 
 static struct {
@@ -68,6 +105,7 @@ static struct {
 	{ PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" },
 	{ PCI_DID_INTEL_ARL_H_GT2_1, "ArrowLake-H GT2" },
 	{ PCI_DID_INTEL_ARL_H_GT2_2, "ArrowLake-H GT2" },
+	{ PCI_DID_INTEL_ARL_HX_GT2, "ArrowLake-HX GT2" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)

src/soc/intel/meteorlake/chip.h

@@ -46,6 +46,9 @@ struct ibecc_config {
 enum soc_intel_meteorlake_power_limits {
 	MTL_P_282_242_CORE,
 	MTL_P_682_482_CORE,
+	ARL_HX_8_16_55W_CORE,
+	ARL_HX_8_12_55W_CORE,
+	ARL_HX_6_8_55W_CORE,
 	MTL_POWER_LIMITS_COUNT
 };
 
@@ -54,6 +57,7 @@ enum soc_intel_meteorlake_cpu_tdps {
 	TDP_15W = 15,
 	TDP_28W = 28,
 	TDP_45W = 45,
+	TDP_55W = 55,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -69,6 +73,9 @@ static const struct {
 	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W },
 	{ PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_45W },
 	{ PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W },
+	{ PCI_DID_INTEL_ARL_HX_ID_1, ARL_HX_8_16_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_ARL_HX_ID_2, ARL_HX_8_12_55W_CORE, TDP_55W },
+	{ PCI_DID_INTEL_ARL_HX_ID_3, ARL_HX_6_8_55W_CORE, TDP_55W },
 };
 
 /* Types of display ports */