updates for working with next svd2rust release#540
updates for working with next svd2rust release#540bors[bot] merged 3 commits intostm32-rs:masterfrom burrbull:update
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@adamgreig rebased |
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Thanks for working through this! I need to check some of the G0 ones a bit more carefully, but otherwise the main question is about all the F7 and L4 |
| WS12: [12, "12 wait states"] | ||
| WS13: [13, "13 wait states"] | ||
| WS14: [14, "14 wait states"] | ||
| WS15: [15, "15 wait states"] |
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Do we even need this latency16 file? Looks like all users of flash_v1.yaml use the flash_latency8.yaml version.
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Looks like I planned to do something, but forgot.
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According to RM only 405/415 407/417 series in STM32F4 don't support higher states.
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I've finished reviewing and I guess it makes sense to merge this before tackling #546 since it's based off it. My only outstanding question really is about the commented-out CCMR files, what do you think?
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The comments of CCMR files is fast fix to make compile, as currently those files are broken. |
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Thank you very much for working this out!
Understood about CCR being fixed in #546.
I've just noticed on a second review that the F7x2's rebase of TIM5 to use TIM2 means its option register is no longer correct, but let's fix that in another PR. Everything else LGTM, thanks for fixing the flash latency bits.
bors merge
rust-embedded/svd2rust#508