A debug and test environment for AXI-Stream based ethernet frame processing in FPGAs.
Developed for the Ultrascale+ series of AMD. Potentially portable to other environments. Tested e.g. on ZCU102 and KR260 boards and in Simulation mode in Vivado.
Verilog IPs with testbench to create and record a 32Bit AXI-Stream from BRAM.
Python scripts to create BRAM data for playback and convert recorded data back to a .pcap file.