Split out SMP examples

.cargo/config.toml

@@ -1,56 +0,0 @@
-[target.armv8r-none-eabihf]
-# Note, this requires QEMU 9 or higher
-runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv8r-none-eabihf]
-# Note, this requires QEMU 9 or higher
-runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"
-
-[target.armv7r-none-eabihf]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"
-
-[target.thumbv7r-none-eabihf]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"
-
-[target.armv7r-none-eabi]
-# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
-# qemu-system-arm will lock up
-runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv7r-none-eabi]
-# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
-# qemu-system-arm will lock up
-runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"
-
-[target.armv7a-none-eabihf]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv7a-none-eabihf]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
-
-[target.armv7a-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv7a-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
-
-[target.armv6-none-eabihf]
-runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
-
-[target.armv6-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv6-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
-
-[target.armv5te-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv5te-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
-
-[target.armv4t-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
-
-[target.thumbv4t-none-eabi]
-runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

.gitignore

@@ -1,6 +1,8 @@
 target
 examples/mps3-an536/target
 examples/mps3-an536/target-d32
+examples/mps3-an536-smp/target
+examples/mps3-an536-smp/target-d32
 examples/versatileab/target
 examples/versatileab/target-d32
 Cargo.lock

.vscode/settings.json

@@ -7,7 +7,9 @@
     "rust-analyzer.checkOnSave": true,
     "rust-analyzer.linkedProjects": [
         "./Cargo.toml",
+        "./arm-targets/Cargo.toml",
         "examples/versatileab/Cargo.toml",
-        "examples/mps3-an536/Cargo.toml"
+        "examples/mps3-an536/Cargo.toml",
+        "examples/mps3-an536-smp/Cargo.toml",
     ]
 }

Cargo.toml

@@ -3,6 +3,7 @@ exclude = [
   "arm-targets",
   "examples/versatileab",
   "examples/mps3-an536",
+  "examples/mps3-an536-smp",
 ]
 members = [
   "aarch32-cpu",

aarch32-rt/link.x

@@ -1,11 +1,41 @@
 /*
 Basic AArch32 linker script.
 
-You must supply a file called `memory.x` which defines the memory regions
-'VECTORS', 'CODE', 'DATA', 'STACKS'.
+You must supply a file called `memory.x` in your linker search path. It must
+define Region Aliases 'VECTORS', 'CODE', 'DATA', 'STACKS'.
 
-The stacks will be at the top of the STACKS region by default, use `_pack_stacks`
-to overwrite default behaviour.
+Here is an example `memory.x` file:
+
+-------------
+MEMORY {
+    FLASH : ORIGIN = 0x08000000, LENGTH = 2M
+    SRAM  : ORIGIN = 0x10000000, LENGTH = 512K
+}
+
+REGION_ALIAS("VECTORS", FLASH);
+REGION_ALIAS("CODE", FLASH);
+REGION_ALIAS("DATA", SRAM);
+REGION_ALIAS("STACKS", SRAM);
+-------------
+
+The AArch32 platform uses seven separate stacks. The default sizes for each are
+given at the bottom of this file. However, your `memory.x` can provide an
+alternative size for any (or all) of them, provided that size is a multiple of
+eight bytes. For example, your `memory.x` might include:
+
+-------------
+PROVIDE(_und_stack_size = 3456);
+PROVIDE(_svc_stack_size = 3456);
+PROVIDE(_abt_stack_size = 3456);
+PROVIDE(_hyp_stack_size = 3456);
+PROVIDE(_irq_stack_size = 3456);
+PROVIDE(_fiq_stack_size = 3456);
+PROVIDE(_sys_stack_size = 3456);
+-------------
+
+The stacks will be located at the top of the STACKS region by default. Use
+`PROVIDE(_pack_stacks = 0)` to remove the padding and locate the stacks at the
+bottom of that region instead.
 
 Based upon the linker script from https://github.com/rust-embedded/cortex-m
 */
@@ -18,26 +48,55 @@ EXTERN(_start);
 EXTERN(_default_handler);
 
 SECTIONS {
+    /* # Vector Table
+     *
+     * Our ARM interrupt vector table, consisting of branch instructions to
+     * each exception handler.
+     *
+     * May include FIQ handler code at the end.
+     */
     .vector_table ORIGIN(VECTORS) : {
-        /* The vector table must come first */
         *(.vector_table)
     } > VECTORS
 
+    /* # Text
+     *
+     * Our executable code.
+     */
     .text : {
-        /* Now the rest of the code */
+        __stext = .;
+
         *(.text .text*)
+
+        __etext = .;
     } > CODE
 
+    /* # Text
+     *
+     * Our constants.
+     */
     .rodata : {
+        __srodata = .;
+
         *(.rodata .rodata*)
+
+        __erodata = .;
     } > CODE
 
+    /* # Data
+     *
+     * Our global variables that are not initialised to zero.
+     */
     .data : ALIGN(4) {
         . = ALIGN(4);
         __sdata = .;
+
         *(.data .data.*);
+
         . = ALIGN(4);
+        /* NB: __edata defined lower down */
     } > DATA AT>CODE
+
     /*
      * Allow sections from user `memory.x` injected using `INSERT AFTER .data` to
      * use the .data loading mechanism by pushing __edata. Note: do not change
@@ -49,28 +108,49 @@ SECTIONS {
     /* LMA of .data */
     __sidata = LOADADDR(.data);
 
+    /* # Block Starting Symbol (BSS)
+     *
+     * Our global variables that *are* initialised to zero.
+     */
     .bss (NOLOAD) : ALIGN(4) {
         . = ALIGN(4);
         __sbss = .;
+
         *(.bss .bss* COMMON)
+
         . = ALIGN(4);
+        /* NB: __ebss defined lower down */
     } > DATA
+
     /*
      * Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to
      * use the .bss zeroing mechanism by pushing __ebss. Note: do not change
      * output region or load region in those user sections!
      */
     __ebss = .;
 
+    /* # Uninitialised Data
+     *
+     * Our global variables that have no defined initial value.
+     */
     .uninit (NOLOAD) : ALIGN(4)
     {
         . = ALIGN(4);
         __suninit = .;
+
         *(.uninit .uninit.*);
+
         . = ALIGN(4);
         __euninit = .;
     } > DATA
 
+
+    /* # Stack Padding
+     *
+     * A padding region to push the stacks to the top of the STACKS region.
+     * If `_pack_stacks == 0`, this is forced to be zero size, putting the
+     * stacks at the bottom of the STACK region.
+     */
     .filler (NOLOAD) : {
         /* Move the .stacks section to the end of the STACKS memory region */
         _next_region = ORIGIN(STACKS) + LENGTH(STACKS);
@@ -80,61 +160,81 @@ SECTIONS {
         . = _start_stacks;
     } > STACKS
 
+    /* # Stacks
+     *
+     * Space for all seven stacks.
+     */
     .stacks (NOLOAD) : ALIGN(8)
     {
         . = ALIGN(8);
+
+        /* Lowest address of allocated stack */
         _stacks_low_end = .;
-        _sys_stack_end = .;
-        . += _sys_stack_size;
-        . = ALIGN(8);
-        _sys_stack = .;
-        _fiq_stack_end = .;
-        . += _fiq_stack_size;
-        . = ALIGN(8);
-        _fiq_stack = .;
-        _irq_stack_end = .;
-        . += _irq_stack_size;
-        . = ALIGN(8);
-        _irq_stack = .;
-        _abt_stack_end = .;
-        . += _abt_stack_size;
-        . = ALIGN(8);
-        _abt_stack = .;
-        _svc_stack_end = .;
-        . += _svc_stack_size;
-        . = ALIGN(8);
-        _svc_stack = .;
-        _und_stack_end = .;
-        . += _und_stack_size;
-        . = ALIGN(8);
-        _und_stack = .;
-        _hyp_stack_end = .;
-        . += _hyp_stack_size;
-        . = ALIGN(8);
-        _hyp_stack = .;
+
+        /* Stack for UND mode */
+        _und_stack_low_end = .;
+        . += (_und_stack_size * _num_cores);
+        _und_stack_high_end = .;
+
+        /* Stack for SVC mode */
+        _svc_stack_low_end = .;
+        . += (_svc_stack_size * _num_cores);
+        _svc_stack_high_end = .;
+
+        /* Stack for ABT mode */
+        _abt_stack_low_end = .;
+        . += (_abt_stack_size * _num_cores);
+        _abt_stack_high_end = .;
+
+        /* Stack for HYP mode */
+        _hyp_stack_low_end = .;
+        . += (_hyp_stack_size * _num_cores);
+        _hyp_stack_high_end = .;
+
+        /* Stack for IRQ mode */
+        _irq_stack_low_end = .;
+        . += (_irq_stack_size * _num_cores);
+        _irq_stack_high_end = .;
+
+        /* Stack for FIQ mode */
+        _fiq_stack_low_end = .;
+        . += (_fiq_stack_size * _num_cores);
+        _fiq_stack_high_end = .;
+
+        /* Stack for SYS mode */
+        _sys_stack_low_end = .;
+        . += (_sys_stack_size * _num_cores);
+        _sys_stack_high_end = .;
+
+        /* Highest address of allocated stack */
         _stacks_high_end = .;
     } > STACKS
 
     /DISCARD/ : {
+        /* Discard any notes */
         *(.note .note*)
+
         /* Discard these unwinding/exception related symbols, they are not used */
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
         /* Discard these exception related symbols, they are not used */
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     }
 }
 
-/* We provide default sizes for the stacks to be overwritten in memory.x */
-PROVIDE(_stack_top = _stacks_high_end); /* deprecated, use _xxx_stack labels as defined in .stacks section */
-PROVIDE(_hyp_stack_size = 0x400);
-PROVIDE(_und_stack_size = 0x400);
-PROVIDE(_svc_stack_size = 0x400);
-PROVIDE(_abt_stack_size = 0x400);
-PROVIDE(_irq_stack_size = 0x400);
-PROVIDE(_fiq_stack_size = 0x400);
-PROVIDE(_sys_stack_size = 0x2000);
-PROVIDE(_pack_stacks = 0); /* set this to 1 to remove the filler section pushing the stacks to the end of STACKS. */
+/* We provide default sizes for the stacks for any not specified in memory.x (which was loaded first) */
+PROVIDE(_und_stack_size = 16K);
+PROVIDE(_svc_stack_size = 16K);
+PROVIDE(_abt_stack_size = 16K);
+PROVIDE(_hyp_stack_size = 16K);
+PROVIDE(_irq_stack_size = 64);
+PROVIDE(_fiq_stack_size = 64);
+PROVIDE(_sys_stack_size = 16K);
+/* Default to one CPU core (i.e. one copy of each stack) */
+PROVIDE(_num_cores      = 1);
 
+/* Set this to 1 in memory.x to remove the filler section pushing the stacks to the end of STACKS. */
+PROVIDE(_pack_stacks = 0);
 
 /* Weak aliases for ASM default handlers */
 PROVIDE(_start                      = _default_start);
@@ -143,6 +243,7 @@ PROVIDE(_asm_svc_handler            = _asm_default_svc_handler);
 PROVIDE(_asm_hvc_handler            = _asm_default_hvc_handler);
 PROVIDE(_asm_prefetch_abort_handler = _asm_default_prefetch_abort_handler);
 PROVIDE(_asm_data_abort_handler     = _asm_default_data_abort_handler);
+/* TODO: Hyp handler goes here */
 PROVIDE(_asm_irq_handler            = _asm_default_irq_handler);
 PROVIDE(_asm_fiq_handler            = _asm_default_fiq_handler);
 
@@ -152,5 +253,26 @@ PROVIDE(_svc_handler            = _default_handler);
 PROVIDE(_hvc_handler            = _default_handler);
 PROVIDE(_prefetch_abort_handler = _default_handler);
 PROVIDE(_data_abort_handler     = _default_handler);
+/* TODO: Hyp handler goes here */
 PROVIDE(_irq_handler            = _default_handler);
-/* There is no default C-language FIQ handler */
+/* NB: There is no default C-language FIQ handler */
+
+/* Check the stack sizes are all a multiple of eight bytes */
+ASSERT(_und_stack_size % 8 == 0, "
+ERROR(aarch32-rt): UND stack size (_und_stack_size) is not a multiple of 8 bytes");
+ASSERT(_svc_stack_size % 8 == 0, "
+ERROR(aarch32-rt): SVC stack size (_svc_stack_size) is not a multiple of 8 bytes");
+ASSERT(_abt_stack_size % 8 == 0, "
+ERROR(aarch32-rt): ABT stack size (_abt_stack_size) is not a multiple of 8 bytes");
+ASSERT(_hyp_stack_size % 8 == 0, "
+ERROR(aarch32-rt): HYP stack size (_hyp_stack_size) is not a multiple of 8 bytes");
+ASSERT(_irq_stack_size % 8 == 0, "
+ERROR(aarch32-rt): IRQ stack size (_irq_stack_size) is not a multiple of 8 bytes");
+ASSERT(_fiq_stack_size % 8 == 0, "
+ERROR(aarch32-rt): FIQ stack size (_fiq_stack_size) is not a multiple of 8 bytes");
+ASSERT(_sys_stack_size % 8 == 0, "
+ERROR(aarch32-rt): SYS stack size (_sys_stack_size) is not a multiple of 8 bytes");
+ASSERT(_num_cores != 0, "
+ERROR(aarch32-rt): Number of cores cannot be zero");
+
+/* End of file */