Found running the origins flow on real input via Jacquard's RTL on-ramp, which uses the patched stack (gpu-eda/yowasp-yosys → robtaylor/yosys@src-retention-y-ext → robtaylor/abc@origin-tracking-clean). Logging here since this repo is the real-world harness for berkeley-abc/abc#487.
Symptom
A design that reaches abc_new with no primary inputs and no primary outputs hard-traps:
16. Executing ABC_NEW pass.
...
27: 0x116f4 - <unknown>!<wasm function 27>: wasm trap: wasm `unreachable` instruction executed
The invocation (from Jacquard's synth.rs):
scratchpad -set abc9.origins_max 100
abc_new -script +&dch,-f;&nf -liberty aigpdk_nomem.lib
Minimal reproducer
module noports_constclk ();
wire a = 0; wire b = 0; reg q = 0;
always_ff @(posedge a) q <= b;
endmodule
(This is chipsalliance/sv-tests tests/chapter-9/9.2.2.4--always_ff.sv, an expected-pass test. slang reports Build succeeded: 0 errors, 0 warnings; the design then optimizes away because nothing is observable.)
Bisected: the trigger is zero primary I/O
Not the constant clock, and not "empty design" — both of my first two hypotheses were wrong:
| variant |
ports |
clock |
result |
| as above |
none |
const |
TRAP |
+ output reg q |
1 out |
const |
fine |
+ input a as clock, no output |
1 in |
real |
fine |
input a, input b, output reg q |
2 in, 1 out |
real |
fine |
- The constant clock is irrelevant — the
output reg q variant keeps the same dead constant clock and survives.
- "Empty" isn't it either — that surviving variant synthesizes to 0 mapped cells (just
assign q = 1'h0) and does not trap.
One port of either direction is enough to avoid it. So abc9 appears to be handed a network with 0 PIs, 0 POs, 0 nodes, and &dch,-f;&nf hits unreachable on it.
Open question: is this ours or stock?
Unknown, and it matters — if &origins isn't implicated, this shouldn't go anywhere near #487.
I tried to A/B against a stock YoWASP wheel and the comparison is blocked, which is worth recording on its own: stock yowasp-yosys 0.67 won't load under the consumer's wasmtime config —
failed to parse WebAssembly module: exception refs not supported without
the exception handling feature (at offset 0x50)
— so it ran 0 passes and never reached abc_new. It failed for an unrelated reason, not because it's immune.
Ways to settle it:
- build a stock-abc wasm from this flake (same wasmtime feature set) and run the reproducer, or
- run the reproducer against native stock abc with
&dch,-f;&nf on an empty network, outside wasm entirely.
If stock also traps, it's an upstream empty-network bug and belongs to berkeley-abc rather than #487. If only the patched abc traps, it's the origins work and should be fixed before #487 lands.
Severity
Low for real designs — a portless module is testbench-shaped, and any real DUT has ports. Its practical effects are:
Downstream tracking: gpu-eda/Jacquard#211.
Found running the origins flow on real input via Jacquard's RTL on-ramp, which uses the patched stack (
gpu-eda/yowasp-yosys→robtaylor/yosys@src-retention-y-ext→robtaylor/abc@origin-tracking-clean). Logging here since this repo is the real-world harness for berkeley-abc/abc#487.Symptom
A design that reaches
abc_newwith no primary inputs and no primary outputs hard-traps:The invocation (from Jacquard's
synth.rs):Minimal reproducer
(This is
chipsalliance/sv-teststests/chapter-9/9.2.2.4--always_ff.sv, an expected-pass test.slangreportsBuild succeeded: 0 errors, 0 warnings; the design then optimizes away because nothing is observable.)Bisected: the trigger is zero primary I/O
Not the constant clock, and not "empty design" — both of my first two hypotheses were wrong:
+ output reg q+ input aas clock, no outputinput a, input b, output reg qoutput reg qvariant keeps the same dead constant clock and survives.assign q = 1'h0) and does not trap.One port of either direction is enough to avoid it. So
abc9appears to be handed a network with 0 PIs, 0 POs, 0 nodes, and&dch,-f;&nfhitsunreachableon it.Open question: is this ours or stock?
Unknown, and it matters — if
&originsisn't implicated, this shouldn't go anywhere near #487.I tried to A/B against a stock YoWASP wheel and the comparison is blocked, which is worth recording on its own: stock
yowasp-yosys0.67 won't load under the consumer'swasmtimeconfig —— so it ran 0 passes and never reached
abc_new. It failed for an unrelated reason, not because it's immune.Ways to settle it:
&dch,-f;&nfon an empty network, outside wasm entirely.If stock also traps, it's an upstream empty-network bug and belongs to berkeley-abc rather than #487. If only the patched abc traps, it's the origins work and should be fixed before #487 lands.
Severity
Low for real designs — a portless module is testbench-shaped, and any real DUT has ports. Its practical effects are:
chipsalliance/sv-testsas a corpus (its tests are overwhelmingly portless compile-only modules); and<wasm function 32210>with nothing indicating synthesis failed. That's being fixed consumer-side (synth: abc_new wasm-traps on a design that optimizes to empty gpu-eda/Jacquard#211), but a clean abc-side error would be better than a trap regardless.Downstream tracking: gpu-eda/Jacquard#211.