origin-shell

Every gate in your sky130 GDS came from a line of RTL — but normally that thread snaps at synthesis and you never see it again. This little Nix flake keeps it alive: it wraps LibreLane with three patched tools so that Verilog \src source locations survive standard-cell mapping, and every mapped gate can point back at the RTL line it came from. Combinational, sequential, and memory designs all land at ~100% coverage, at roughly the same area/timing as the stock flow.

Want the story rather than the manual?

• The thinking / why → SRC-TRACKING-POC.md — what I was after, what I learned, and where this could go (post-PnR provenance).
• The full design & details → DESIGN-stdcell-origin-tracking.md — every per-pass fix, the QoR numbers, the maintainer correspondence.
• Where things stand → HANDOFF.md.

What's in the box

The flake takes LibreLane 3.1.0.dev1's devshell and swaps in three patched tools; everything else (OpenROAD, Magic, KLayout, OpenSTA, the librelane python package) comes unchanged from upstream, so the heavy bits still come from the binary caches.

Tool	Source	What it adds
abc	robtaylor/abc @ origin-tracking-clean	berkeley-abc/abc PR #487 — per-object origin tracking (vOrigins, &origins) carried through optimization + &nf mapping
yosys	robtaylor/yosys @ src-retention-y-ext	\src retention through the abc9 / XAIGER "y" flow, plus \src fixes in FF unmap and memory lowering
librelane	robtaylor/librelane @ origin-tracking-stdcell	a SYNTH_ABC_BACKEND toggle (classic | origins) to pick the provenance-preserving path

Build it

nix build .#librelane      # the whole patched LibreLane (what you usually want)
nix develop                # a shell with the patched yosys + abc on PATH
nix build .#yosys          # just the patched yosys
nix build .#abc            # just the PR #487 abc

The non-yosys/abc tools are cached — point Nix at the FOSSi cache so it doesn't rebuild OpenROAD from scratch:

nix build .#librelane \
  --extra-substituters https://nix-cache.fossi-foundation.org \
  --extra-trusted-public-keys "nix-cache.fossi-foundation.org:3+K59iFwXqKsL7BNu6Guy0v+uTlwsxYQxjspXzqLYQs="

Use it on your own design

Flip one switch in your design's config.json and run LibreLane as normal (with PDK_ROOT pointing at your volare/ciel PDK):

{
    "DESIGN_NAME": "my_design",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_PORT": "clk",
    "CLOCK_PERIOD": 10,
    "SYNTH_ABC_BACKEND": "origins"   // "classic" (the default) = stock behaviour
}

PDK_ROOT=~/.volare ./result/bin/librelane --to Yosys.Synthesis config.json

The synthesized netlist's standard cells now carry \src attributes tracing back to the RTL. Under the hood, origins runs std-cell mapping over XAIGER (via abc_new with a +&dch,-f;&nf script) instead of the classic BLIF path that throws the provenance away.

See it for yourself

There are two harnesses under test/ (more in test/README.md):

# End-to-end area + timing, origins vs classic, on the bundled designs:
PDK_ROOT=~/.volare bash test/qor_compare.sh

# A quick \src-coverage check without the full flow. Needs a yosys built with
# ABCEXTERNAL pointing at the patched abc (make -C ../yosys ABCEXTERNAL=$(pwd)/../abc/build/abc):
YOSYS=../yosys/yosys \
LIB=~/.volare/volare/sky130/versions/*/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib \
  bash test/src_coverage.sh

You should see ~100% \src on every bundled design with origins, and ~0% with classic — that contrast is the whole point.

How the flake pulls it off

yosys is rebuilt from source and told to exec the external abc via the Makefile's ABCEXTERNAL knob. With that set, yosys doesn't build its in-tree yosys-abc at all, so the entire synthesis path quietly uses the origin-tracking abc — no -exe plumbing needed. The overlay overrides yosys and abc-verifier on LibreLane's composed package set (.extend originOverlay), and because .extend rebuilds the fixpoint, yosys.withPlugins and the librelane python package pick up the patched yosys for free.

One wrinkle: this abc is newer than nixpkgs' v0.55, and its CMakeLists.txt fetches googletest over the network at configure time — which the Nix sandbox blocks. -DABC_SKIP_TESTS=ON skips that.

Bumping the pins

The sources are pinned in flake.lock to the pushed branch tips:

nix flake update abc-src yosys-src librelane   # or just `nix flake update` for all

Watch out for the flake-pin trap: after you push a new commit to one of the fork branches, you have to bump its pin, or the flake happily keeps building the old rev. This bit me — LibreLane silently ran a pre-fix yosys for a while.

Want to hack on the tools locally instead? Point the inputs at path:../yosys / path:../abc (flake = false) in flake.nix.