update model_test.h RVMODEL MSW and MTIMER templates for spike and sail to match riscv-isa-sim model_test.h#106
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currently MSW and MTIMER macros aren't functional. Updating to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
updating sail_cSim template to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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requires riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 To include these tests in riscof testlist flow, add Smclint to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclint Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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Jun 6, 2024
This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond
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to dansmathers/riscv-arch-test
that referenced
this pull request
Jun 6, 2024
his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond
pushed a commit
to dansmathers/riscv-arch-test
that referenced
this pull request
Jun 6, 2024
This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
jamesbeyond
pushed a commit
to dansmathers/riscv-arch-test
that referenced
this pull request
Jun 6, 2024
This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Smclic To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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update model_test.h RVMODLE MSW/MTIMER macros to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h
Currently RVMODEL_SET_MSW_INT, RVMODEL_CLEAR_MSW_INT, RVMODEL_SET_MTIMER_INT, RVMODEL_CLEAR_MTIMER_INT aren't used by any architecture tests. This pull updates their functionality to work with sail/spike CLINT models so future interrupt tests can use the macros to set and clear interrupts.