OPENMSP430 for Avnet lx9 microbard
===================================

This whole project is based on the  xilinx_diligent_s3board implementation of the OpenMSP430 Open core by Olivier Girard.


Setup
------

Port 3[0:3] are the red LEDs of the board.
Port 4[0:4] are the switches of the board.
The reset button is the PRG_RST button.
p1_dout[1] and p2_din[2] is mapped to the uart.
The main clock is connected to 20Mhz.


Debug
------
The debug port is mapped to the same uart, to enable it, connect J5 PMOD 4 to ground (This will disable p1_dout[1] and p2_din[2).
There is a instantiation of Chipscope... modify it to fit your purposes.
The clock is connected to J5 PMOD 0. (If you want to see it with a scope)


Use
----
1) Download the project to the fpga
2) Connect J5 PMOD4 to gnd
3) Download the elf
4) Disconnect J5 PMOD4
5) Press reset


Copyright
---------
This port has been done by Ricardo Ribalda <ricardo.ribalda <AT> gmail DOT com>. Feel free to use it, modify it, and distribute it under the original license by Olivier Girard.