Enable ETR and CTCU devices for Monaco#583
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PR #583 — validate-patchPR: #583
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PR #583 — checker-log-analyzerPR: #583
Detailed report: Full report
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PR #583 — validate-patchPR: #583
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PR #583 — checker-log-analyzerPR: #583
Detailed report: Full report
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The CTCU device for monaco shares the same configurations as SA8775p. Add a fallback to enable the CTCU for monaco to utilize the compitable of the SA8775p. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-1-92ff83201584@oss.qualcomm.com [ upstream commit 51cd1fb ]
Add CTCU and ETR nodes in DT to enable expected functionalities. Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-2-92ff83201584@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> [ upstream commit 4f791e0 ]
…icator Fix the wrong connection for the qdss replicator device. Link: https://lore.kernel.org/all/20260428-fix-monaco-coresight-dt-v2-1-2293259bbd10@oss.qualcomm.com/ Fixes: 4f791e0 ("arm64: dts: qcom: monaco: Add CTCU and ETR nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Test Matrix
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LAVA Failed Case Triage SummaryPR: #583 Job 100412 | SoC unknown_soc_job100412LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100412 No failed cases detected from the LAVA results section. Job 100413 | SoC unknown_soc_job100413LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100413 No failed cases detected from the LAVA results section. Job 100414 | SoC unknown_soc_job100414LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100414 No failed cases detected from the LAVA results section. Job 100415 | SoC unknown_soc_job100415LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100415 No failed cases detected from the LAVA results section. Job 100416 | SoC unknown_soc_job100416LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100416 No failed cases detected from the LAVA results section. Job 100417 | SoC unknown_soc_job100417LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100417 No failed cases detected from the LAVA results section. Job 100418 | SoC unknown_soc_job100418LAVA job: https://lava-oss.qualcomm.com/scheduler/job/100418 No failed cases detected from the LAVA results section. |
LAVA Failed Case Triage SummaryPR: #583 Job 98029 | SoC kaanapali-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98029 Failed test cases in LAVA job 98029 (SoC: kaanapali-mtp).
Job 98030 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98030 Failed test cases in LAVA job 98030 (SoC: qcs615-ride).
Job 98031 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98031 Failed test cases in LAVA job 98031 (SoC: qcs9100-ride).
Job 98032 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98032 Failed test cases in LAVA job 98032 (SoC: qcs8300-ride).
Job 98033 | SoC sm8750-mtpLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98033 Failed test cases in LAVA job 98033 (SoC: sm8750-mtp).
Job 98034 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98034 Failed test cases in LAVA job 98034 (SoC: monaco-evk).
Job 98035 | SoC glymur-crdLAVA job: https://lava-oss.qualcomm.com/scheduler/job/98035 Failed test cases in LAVA job 98035 (SoC: glymur-crd).
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Test Matrix
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LAVA Failed Case Triage SummaryPR: #583 Job 101033 | SoC qcs615-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/101033 Failed test cases in LAVA job 101033 (SoC: qcs615-ride).
Job 101034 | SoC qcs6490-rb3gen2LAVA job: https://lava-oss.qualcomm.com/scheduler/job/101034 Failed test cases in LAVA job 101034 (SoC: qcs6490-rb3gen2).
Job 101035 | SoC qcs9100-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/101035 Failed test cases in LAVA job 101035 (SoC: qcs9100-ride).
Job 101036 | SoC monaco-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/101036 Failed test cases in LAVA job 101036 (SoC: monaco-evk).
Job 101037 | SoC qcs8300-rideLAVA job: https://lava-oss.qualcomm.com/scheduler/job/101037 Failed test cases in LAVA job 101037 (SoC: qcs8300-ride).
Job 101038 | SoC x1e80100LAVA job: https://lava-oss.qualcomm.com/scheduler/job/101038 Failed test cases in LAVA job 101038 (SoC: x1e80100).
Job 101039 | SoC lemans-evkLAVA job: https://lava-oss.qualcomm.com/scheduler/job/101039 Failed test cases in LAVA job 101039 (SoC: lemans-evk).
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Patchset 1 adds DT nodes for enabling CTCU and ETR devices.
Patchset 2 fixes a wrong connection bug that is introduced by Patchset1.
CRs-Fixed: 4537337