Skip to content

drm/msm/a6xx: Add support for A704 GPU and dt-bindings: display/msm/gpu: Add support for A704 shikra GPU #1172

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
asherawa wants to merge 2 commits into
base: early/hwe/shikra/drivers
Choose a base branch
from
+37 −8
Open

drm/msm/a6xx: Add support for A704 GPU and dt-bindings: display/msm/gpu: Add support for A704 shikra GPU #1172

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
2781b50
drm/msm/adreno: Add support for A704 GPU
asherawa Apr 21, 2026
8a81963
dt-bindings: display/msm/gpu: Add support for A704 shikra GPU
asherawa May 14, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/display/msm/gpu.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -357,6 +357,7 @@ allOf:
- qcom,adreno-610.0
- qcom,adreno-619.1
- qcom,adreno-07000200
- qcom,adreno-07000400
then:
properties:
clocks:
Expand Down
18 changes: 18 additions & 0 deletions drivers/gpu/drm/msm/adreno/a6xx_catalog.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1477,6 +1477,24 @@ static const struct adreno_info a7xx_gpus[] = {
{ 178, 2 },
{ 142, 3 },
),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x07000400),
.family = ADRENO_6XX_GEN1, /* NOT a mistake! */
.fw = {
[ADRENO_FW_SQE] = "a702_sqe.fw",
},
.gmem = SZ_128K,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_HW_APRIV,
.funcs = &a6xx_gmuwrapper_funcs,
.zapfw = "a704_zap.mdt",
.a6xx = &(const struct a6xx_info) {
.hwcg = a702_hwcg,
.protect = &a650_protect,
.gbif_cx = a640_gbif,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x0000c000,
},
}, {
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
.family = ADRENO_7XX_GEN1,
Expand Down
18 changes: 11 additions & 7 deletions drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -643,7 +643,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
clock_cntl_on = 0x8aa8aa02;
else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu))
clock_cntl_on = 0xaaa8aa82;
else if (adreno_is_a702(adreno_gpu))
else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu))
clock_cntl_on = 0xaaaaaa82;
else
clock_cntl_on = 0x8aa8aa82;
Expand Down Expand Up @@ -793,7 +793,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_7c3(gpu))
cfg->highest_bank_bit = 14;

if (adreno_is_a702(gpu))
if (adreno_is_a702(gpu) || adreno_is_a704(gpu))
cfg->highest_bank_bit = 14;

if (cfg->highest_bank_bit != common_cfg->highest_bank_bit)
Expand Down Expand Up @@ -832,7 +832,8 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
uavflagprd_inv = 2;

if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu) ||
adreno_is_a704(adreno_gpu))
min_acc_len_64b = true;

gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
Expand Down Expand Up @@ -1067,7 +1068,8 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
return false;

/* A7xx is safe! */
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) ||
adreno_is_a704(adreno_gpu) || adreno_is_a8xx(adreno_gpu))
return true;

/*
Expand Down Expand Up @@ -1350,6 +1352,7 @@ static int hw_init(struct msm_gpu *gpu)

if (!(adreno_is_a650_family(adreno_gpu) ||
adreno_is_a702(adreno_gpu) ||
adreno_is_a704(adreno_gpu) ||
adreno_is_a730(adreno_gpu))) {
gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M;

Expand Down Expand Up @@ -1385,7 +1388,7 @@ static int hw_init(struct msm_gpu *gpu)
if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
} else if (adreno_is_a702(adreno_gpu)) {
} else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu)) {
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64);
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63);
} else if (!adreno_is_a7xx(adreno_gpu))
Expand Down Expand Up @@ -1423,7 +1426,8 @@ static int hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
else if (adreno_is_a619(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu) ||
adreno_is_a704(adreno_gpu))
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
else
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
Expand Down Expand Up @@ -1459,7 +1463,7 @@ static int hw_init(struct msm_gpu *gpu)
else
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
} else if (adreno_is_a702(adreno_gpu)) {
} else if (adreno_is_a702(adreno_gpu) || adreno_is_a704(adreno_gpu)) {
/* Something to do with the HLSQ cluster */
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24));
}
Expand Down
8 changes: 7 additions & 1 deletion drivers/gpu/drm/msm/adreno/adreno_gpu.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -501,13 +501,19 @@ static inline int adreno_is_a702(const struct adreno_gpu *gpu)
return gpu->info->chip_ids[0] == 0x07000200;
}

static inline int adreno_is_a704(const struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x07000400;
}

static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
{
if (WARN_ON_ONCE(!gpu->info))
return false;
return adreno_is_a610(gpu) ||
adreno_is_a612(gpu) ||
adreno_is_a702(gpu);
adreno_is_a702(gpu) ||
adreno_is_a704(gpu);
}

/* TODO: 615/616 */
Expand Down