ARM: dts: msm: Add support for shikra GPU#1170
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The Shikra SoM is a compact compute module integrating the SoC and essential components optimized for IoT applications, designed to mount on carrier boards. Shikra supports three SoM variants: two retail options (with and without modem) and one industrial variant , represented by the following device trees: - shikra-cqm-som.dtsi : Retail SoM with modem - shikra-cqs-som.dtsi : Retail SoM without modem - shikra-iqs-som.dtsi : Industrial SoM without modem Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device trees for the Shikra EVK platform, which combines Shikra SoM with a common carrier board. Introduce DTS files for CQM, CQS and IQS EVK variants: - shikra-cqm-evk.dts - shikra-cqs-evk.dts - shikra-iqs-evk.dts Also add a shared include file, shikra-evk.dtsi, which contains the common daughter card nodes used across Shikra EVK variants. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add the reserved memory nodes for Shikra. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add the apps and adreno smmu node as found in Shikra SoC. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add qcom,shikra-apcs-hmss-global for the APCS mailbox binding. This avoids undocumented-compatible warnings from checkpatch and keeps schema constraints aligned for this target. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add the RPM message RAM SRAM region and APCS HMSS global mailbox controller, and wire them up to a new glink-edge node. The rpm_msg_ram node exposes the shared SRAM used for GLINK FIFOs and includes the apss_mpm sub-node for the MPM sleep counter. The `qcom,glink-rpm` transport uses: - `qcom,rpm-msg-ram` for shared GLINK FIFOs - APCS mailbox channel 0 for kick/notify This enables RPM GLINK-based inter-processor communication on Shikra. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add qfprom node and its properties for Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Move rpm_requests node to under glink-edge node. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Add support for RPMCC and GCC nodes on Shikra platforms. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add spmi-pmic-arb device for the SPMI PMIC arbiter found on shikra. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the RPM SMD power domain controller node for Shikra with a complete OPP table covering all 8 voltage corners from MIN_SVS to TURBO_NO_CPR. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add RPM regulator for the Shikra Retail (CQM/CQS) SOM variants using pm4125-regulators with S1-S4 buck switchers and L1-L22 LDOs, and for the Industrial (IQS) SOM variant using pm8150-regulators with S4-S9 buck switchers and L1-L18 LDOs. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add the watchdog node for Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Describe the TCSR mutex hwlock controller and reference it from the SMEM node to enable proper hardware locking on Shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add interconnect devices for config_noc, system_noc, mc_virt, clk_virt, mem_noc, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Add the SCM firmware node and TCSR syscon required to support download mode on Shikra. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Enable console support for shikra. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Add support for eMMC on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Enable eMMC for shikra CQS, CQM and IQS EVK variants. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Add support for SD card on shikra SoC and enable the required pinctrl configurations. Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
Add usb related changes on Shikra specifically: a) Primary controller node b) Primary high speed phy c) QMP Phy for super speed operation Enable USB controller and phys in device mode on CQS and CQM variants. Add the regulators for the phys accordingly. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Enable primary usb controller on IQS platform in peripheral mode. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Add PMIC topic overlay changes for Shikra SOM variants (CQM, CQS, IQS): - Add pm4125 temp-alarm and VADC channel nodes - Add pm8005 temp-alarm node - Add thermal zones for PMIC and system thermistors - Add GPIO key (volume up) bindings - Add ADC thermal bridge nodes for pa/quiet/msm thermistors - Disable pm8005 regulators across SOM variants - Switch SPMI interrupt to MPM edge-triggered Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add support for DISPCC and GPUCC nodes on Qualcomm Shikra platforms. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add clock entries for adreno smmu node in Shikra. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Enable video en/decoder on the Shikra EVK board. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Enable USB role switching and USB-C orientation handling for the Qualcomm shikra board. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Flip RPMh tags so CPU configuration paths use RPM_ACTIVE_TAG and video memory paths use RPM_ALWAYS_TAG, matching intended power management behavior. Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add a DT node for the Last Level Cache Controller (LLCC) on the Shikra SoC. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's shikra-cqm board. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP and LPAICP for Qualcomm's shikra-cqs board. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP and LPAICP for Qualcomm's shikra-iqs board. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Update reserved memory regions for Shikra aligning with new set of no-map regions. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Fix compatible entries for apps_smmu and adreno_smmu nodes, add missing "qcom,adreno-smmu" compatible entry for adreno_smmu node. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Modify MPM pin count to incorporate all MPM interrupts that can be configured. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Remove unused regulators (s1, s4, l1, l2, l11) and tighten min/max voltage ranges for remaining rails to match actual operating voltages derived from PGA report analysis. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add CX power domain support to GCC node on Shikra platform. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Modify compatible for Shikra mailbox APCS device and add fallback compatible string. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Add DT nodes for the CoreSight debug and trace subsystem on Qualcomm Shikra SoC. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Enable uart8 and add WCN3988 Bluetooth node with board-specific regulator supplies across CQM, CQS and IQS Shikra EVK variants. Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Add the SoC-level display subsystem nodes for Shikra: MDSS wrapper, DPU display controller, DSI host controller, and 14nm DSI PHY. Shikra uses DPU 6.5 hardware (same as QCM2290), with platform-specific compatibles qcom,shikra-dpu and qcom,shikra-dsi-ctrl. The dispcc clock inputs for the DSI byte and pixel PLLs are wired from mdss_dsi0_phy. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Enable the Shikra MDSS display subsystem on the CQM EVK board and add the DLC0697 panel node. Pin pm4125_l5 to 1.232V with regulator-allow-set-load for DSI PHY PLL stability. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Add qcrypto and cryptobam support for shikra target. Link: https://lore.kernel.org/lkml/20260515-shikra_qcrypto-v1-3-80f07b345c29@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add True Random Number Generator(TRNG) node for shikra. Link: https://lore.kernel.org/lkml/20260514-shikra_rng-v1-2-4ea721a1429a@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add UFS inline crypto engine(ICE) support for shikra. Link: https://lore.kernel.org/lkml/20260515-shikra_ice_ufs-v1-2-b1b6ced70559@oss.qualcomm.com Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Add pm4125_s1 regulator node at fixed 1.396V to both shikra-cqm-som and shikra-cqs-som. This rail is used by the audio subsystem. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
Add a separate fixed dummy regulator for Bluetooth. Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Enable the DLC0697 MIPI DSI display panel on the Shikra CQS EVK. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Enable AudioCore Clock Controller (AudioCoreCC) support on Shikra platform. The Shikra CQM variant requires both clock and reset support, while the Shikra CQS variant requires only reset support. Hence, add support to configure the respective device tree nodes accordingly. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add the A704 GPU and GMU wrapper device tree nodes to shikra.dtsi, including register mappings, clock, interconnect, IOMMU, OPP table, and zap shader region. Enable the GPU and set the zap shader firmaware path on all three Shikra board variants (cqm-evk, cqs-evk, iqs-evk). Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
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Add GPU devicetree files for shikra target.