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Add Shikra CAMSS DT nodes and camera overlay #1163

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6cbdf76
arm64: dts: qcom: shikra: Add CAMSS node
May 12, 2026
d48ab5f
arm64: dts: qcom: shikra: Add CCI definitions
May 12, 2026
0c1b126
arm64: dts: qcom: shikra: Add pin configuration for mclks
May 12, 2026
3398f5c
arm64: dts: qcom: shikra-cq-evk-imx577-camera: Add DT overlay
May 13, 2026
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6 changes: 6 additions & 0 deletions arch/arm64/boot/dts/qcom/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -330,6 +330,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb

shikra-cqm-evk-imx577-camera-dtbs := shikra-cqm-evk.dtb shikra-cq-evk-imx577-camera.dtbo
shikra-cqs-evk-imx577-camera-dtbs := shikra-cqs-evk.dtb shikra-cq-evk-imx577-camera.dtbo

dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk-imx577-camera.dtb
dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk-imx577-camera.dtb
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nihal231998 marked this conversation as resolved.
dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
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63 changes: 63 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra-cq-evk-imx577-camera.dtso
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Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/

/dts-v1/;
/plugin/;

#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/gpio/gpio.h>

&camss {
vdd-csiphy-1p2-supply = <&pm4125_l5>;
vdd-csiphy-1p8-supply = <&pm4125_l13>;

status = "okay";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@1 {
reg = <1>;

csiphy1_ep: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&imx577_ep1>;
};
};
};
};

&cci {
status = "okay";
};

&cci_i2c1 {
#address-cells = <1>;
#size-cells = <0>;

camera@1a {
compatible = "sony,imx577";
reg = <0x1a>;

reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&mclk1_default>;
pinctrl-names = "default";

clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
assigned-clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
assigned-clock-rates = <24000000>;

avdd-supply = <&pm4125_l15>;

port {
imx577_ep1: endpoint {
link-frequencies = /bits/ 64 <600000000>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&csiphy1_ep>;
};
};
};
};
195 changes: 195 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -451,6 +451,66 @@
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;

cci_i2c0_default: cci-i2c0-default-state {
/* SDA, SCL */
pins = "gpio36", "gpio37";
function = "cci_i2c0";
drive-strength = <2>;
bias-pull-up = <2200>;
};

cci_i2c0_sleep: cci-i2c0-sleep-state {
/* SDA, SCL */
pins = "gpio36", "gpio37";
function = "cci_i2c0";
drive-strength = <2>;
bias-pull-down;
};

cci_i2c1_default: cci-i2c1-default-state {
/* SDA, SCL */
pins = "gpio41", "gpio42";
function = "cci_i2c1";
drive-strength = <2>;
bias-pull-up = <2200>;
};

cci_i2c1_sleep: cci-i2c1-sleep-state {
/* SDA, SCL */
pins = "gpio41", "gpio42";
function = "cci_i2c1";
drive-strength = <2>;
bias-pull-down;
};

mclk0_default: mclk0-default-state {
pins = "gpio34";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};

mclk1_default: mclk1-default-state {
pins = "gpio35";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};

mclk2_default: mclk2-default-state {
pins = "gpio96";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};

mclk3_default: mclk3-default-state {
pins = "gpio98";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};

qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio2", "gpio3";
Expand Down Expand Up @@ -1341,6 +1401,141 @@
};
};

cci: cci@5c1b000 {
compatible = "qcom,shikra-cci", "qcom,msm8996-cci";

reg = <0x0 0x05c1b000 0x0 0x1000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
<&gcc GCC_CAMSS_CCI_0_CLK>;
clock-names = "ahb",
"cci";

pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>;
pinctrl-names = "default", "sleep";

#address-cells = <1>;
#size-cells = <0>;

status = "disabled";

cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};

cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};

camss: camss@5c11000 {
compatible = "qcom,shikra-camss";

reg = <0x0 0x05c11000 0x0 0x1000>,
<0x0 0x05c6e000 0x0 0x1000>,
<0x0 0x05c75000 0x0 0x1000>,
<0x0 0x05c52000 0x0 0x1000>,
<0x0 0x05c53000 0x0 0x1000>,
<0x0 0x05c66000 0x0 0x400>,
<0x0 0x05c68000 0x0 0x400>,
<0x0 0x05c6f000 0x0 0x4000>,
<0x0 0x05c76000 0x0 0x4000>;
reg-names = "top",
"csid0",
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"csid1",
"csiphy0",
"csiphy1",
"csitpg0",
"csitpg1",
"vfe0",
"vfe1";

clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMSS_AXI_CLK>,
<&gcc GCC_CAMSS_NRT_AXI_CLK>,
<&gcc GCC_CAMSS_RT_AXI_CLK>,
<&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
<&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
<&gcc GCC_CAMSS_CPHY_0_CLK>,
<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
<&gcc GCC_CAMSS_CPHY_1_CLK>,
<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
<&gcc GCC_CAMSS_TOP_AHB_CLK>,
<&gcc GCC_CAMSS_TFE_0_CLK>,
<&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
<&gcc GCC_CAMSS_TFE_1_CLK>,
<&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
clock-names = "ahb",
"axi",
"camnoc_nrt_axi",
"camnoc_rt_axi",
"csi0",
"csi1",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"top_ahb",
"vfe0",
"vfe0_cphy_rx",
"vfe1",
"vfe1_cphy_rx";

interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csiphy0",
"csiphy1",
"csitpg0",
"csitpg1",
"vfe0",
"vfe1";

interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
&config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
<&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
&mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
<&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
&mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
interconnect-names = "ahb",
"hf_mnoc",
"sf_mnoc";

iommus = <&apps_smmu 0x400 0x0>;

power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;

status = "disabled";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
};

port@1 {
reg = <1>;
};
};
};

mdss: display-subsystem@5e00000 {
compatible = "qcom,shikra-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
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