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Add pcie qref regulator for Hamoa IOT EVK platform #1147

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Add pcie qref regulator for Hamoa IOT EVK platform #1147

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aadc04b
WORKAROUND: arm64: dts: qcom: Add qref supply for PCIe PHYs
qianyu-qcom May 14, 2026
81a22e6
WORKAROUND: phy: qcom: qmp-pcie: add x1e80100 qref supplies
qianyu-qcom May 14, 2026
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4 changes: 4 additions & 0 deletions arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -400,6 +400,7 @@
&pcie3_phy {
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
vdda-qref-supply = <&vreg_l3j_0p8>;

status = "okay";
};
Expand All @@ -414,6 +415,7 @@
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
vdda-qref-supply = <&vreg_l3j_0p8>;

status = "okay";
};
Expand All @@ -428,6 +430,7 @@
&pcie5_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
vdda-qref-supply = <&vreg_l3j_0p8>;

status = "okay";
};
Expand All @@ -442,6 +445,7 @@
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
vdda-qref-supply = <&vreg_l3j_0p8>;

status = "okay";
};
Expand Down
16 changes: 8 additions & 8 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4524,8 +4524,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen3x2_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.nocsr_reset_list = sm8550_pciephy_nocsr_reset_l,
.num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
.regs = pciephy_v5_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Expand Down Expand Up @@ -4556,8 +4556,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.nocsr_reset_list = sm8550_pciephy_nocsr_reset_l,
.num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
.regs = pciephy_v6_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Expand Down Expand Up @@ -4591,8 +4591,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.nocsr_reset_list = sm8550_pciephy_nocsr_reset_l,
.num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
.regs = pciephy_v6_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Expand Down Expand Up @@ -4624,8 +4624,8 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.nocsr_reset_list = sm8550_pciephy_nocsr_reset_l,
.num_nocsr_resets = ARRAY_SIZE(sm8550_pciephy_nocsr_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
.regs = pciephy_v6_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Expand Down