feat: add qdb riscv support

[Jvlegod]

Checklist

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• This PR only contains minor fixes.
• This PR contains major feature update.
• This PR introduces a new function/api for Qiling Framework.

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• Essential comments are added.
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• I have added enough tests for this PR.
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---

Feature

b69128f add QDB support for RISC-V 32/64(also with tests).

Fix

718280f fixes trailing register row rendering.

Testing revealed that the issue primarily occurs on ARM Cortex-M and RISC-V 32/64.

For example(ARM Cortex-M):

Before fix:

r0       : 0x00000000	r1       : 0x00000000	r2       : 0x00000000	r3       : 0x00000000
r4       : 0x00000000	r5       : 0x00000000	r6       : 0x00000000	r7       : 0x00000000
r8       : 0x00000000	sb       : 0x00000000	sl       : 0x00000000	fp       : 0x00000000
ip       : 0x00000000	sp       : 0x20020000	lr       : 0xffffffff	pc       : 0x08001308
xpsr     : 0x41000000	control  : 0x00000000	primask  : 0x00000000	basepri  : 0x00000000
[? mode] [flags: thumb fiq irq overflow carry ZERO neg]

After fix:

r0       : 0x00000000	r1       : 0x00000000	r2       : 0x00000000	r3       : 0x00000000
r4       : 0x00000000	r5       : 0x00000000	r6       : 0x00000000	r7       : 0x00000000
r8       : 0x00000000	sb       : 0x00000000	sl       : 0x00000000	fp       : 0x00000000
ip       : 0x00000000	sp       : 0x20020000	lr       : 0xffffffff	pc       : 0x08001308
xpsr     : 0x00000000	control  : 0x00000000	primask  : 0x00000000	basepri  : 0x00000000
faultmask: 0x00000000
[? mode] [flags: thumb fiq irq overflow carry zero neg]

Reason: in ARM Cortex-M:

......
        regs = (
            'r0', 'r1', 'r2', 'r3',
            'r4', 'r5', 'r6', 'r7',
            'r8', 'r9', 'r10', 'r11',
            'r12', 'sp', 'lr', 'pc'
        )
......
class ArchCORTEX_M(ArchARM):
    _flags_reg: ClassVar[str] = 'xpsr'

    def __init__(self):
        super().__init__()

        self._regs += (
            'xpsr', 'control', 'primask',
            'basepri', 'faultmask'
        )

However, 21 % 4 == 1.