fix(opt): f32/f64 ops no longer panic the optimized lowering path (#120)

[avrabe]

Summary

Closes #120. The optimized lowering path (wasm_to_ir → ir_to_arm) panicked with an unmapped-vreg error on any module containing scalar f32/f64 ops. Real customer bug — surfaced on the falcon-rate-component module and on compiler_builtins float::div / gale_compute_ipi_mask, not a fuzz artifact.

Root cause

OptimizerBridge::wasm_to_ir has zero match arms for f32/f64 ops — every float op falls through the _ => Opcode::Nop catch-all. Independently confirmed: the IR Opcode enum (synth-opt) has no float opcodes at all. A value-producing float op emitting Nop produces no vreg, so a downstream consumer references an unmapped vreg and trips the PR #101 defensive get_arm_reg panic in ir_to_arm. Same #93 silent-drop class — for floats.

The non-optimized selector (select_with_stack) does handle f32 via VFP/FPU. Only the optimized path lacked it.

Fix — Option A: decline + fall back

The IR has no float opcodes, so adding them to the optimized path (Option B) would be a large VFP-lowering feature. Instead:

• optimizer_bridge.rs: new is_unsupported_float_op classifier (all scalar f32/f64 arithmetic, comparison, math, conversion, load/store). optimize_full scans its input and returns Err(Error::UnsupportedInstruction(...)) referencing wasm_to_ir: unmapped vreg panic still trips on compiler_builtins (float::div) and gale_compute_ipi_mask after v0.2.1's #97 memset fix #120 if any float op is present.
• arm_backend.rs: compile_wasm_to_arm now catches an Err from optimize_full and falls back to direct selection (select_with_stack), which handles f32. The ISA feature gate still runs — f32 on a no-FPU target still fails cleanly.

The optimized path becomes an opt-in fast path, not a correctness dependency: when it can't handle a module, the more-capable non-optimized selector takes over.

Tests

• regression_issue_120_f32_optimized.rs (new, 5 tests): optimize_full + ir_to_arm on f32.div+store, f32.div+return, assorted f32 ops, f64 ops — all assert clean Err, never panic; plus an i32 guard that the optimized path still works.
• arm_backend.rs (3 new tests): end-to-end Backend::compile_function for f32 div/add/mul/sub on Cortex-M4F via the default optimized config (the exact config that panicked pre-fix) — asserts non-empty machine code; plus a no-FPU rejection test.

Validation: cargo test --workspace --exclude synth-verify 0 failures; clippy clean; fmt clean.

Notes for review

• f64 is still unsupported in both paths. The optimized path now declines it cleanly; select_with_stack doesn't implement f64 either — an f64 module now fails with a clean ISA/selection error instead of panicking, but still won't compile. Adding f64 is separate scope.
• This also helps the fuzz harnesses — fuzz inputs with scalar f32/f64 ops that previously hit the optimizer_bridge.rs panic now take the typed-error fallback path.
• The defensive get_arm_reg panic is untouched — the fix routes float ops away from it, doesn't remove the guard.

Test plan

• CI green
• f32-containing module compiles end-to-end via the default (optimized) config
• f64 module fails cleanly (no panic)

🤖 Generated with Claude Code

[codecov]

Codecov Report

❌ Patch coverage is 97.50000% with 2 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-backend/src/arm_backend.rs	97.14%	2 Missing ⚠️

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