Align shift_reg name with other register modules

Bender.yml

@@ -51,8 +51,8 @@ sources:
       - src/cc_rr_arb_tree.sv
       - src/cc_rstgen_bypass.sv
       - src/cc_serial_deglitch.sv
-      - src/cc_shift_reg.sv
-      - src/cc_shift_reg_gated.sv
+      - src/cc_shift_register.sv
+      - src/cc_shift_register_gated.sv
       - src/cc_spill_register_flushable.sv
       - src/cc_stream_demux.sv
       - src/cc_stream_filter.sv

README.md

@@ -73,8 +73,8 @@ Please note that cells with status *deprecated* are not to be used for new desig
 | [`gray_to_binary`](src/gray_to_binary.sv)                      | Gray code to binary converter                                                                             | active       |                                     |
 | [`lzc`](src/lzc.sv)                                            | Leading/trailing-zero counter                                                                             | active       |                                     |
 | [`onehot_to_bin`](src/onehot_to_bin.sv)                        | One-hot to binary converter                                                                               | active       |                                     |
-| [`shift_reg`](src/shift_reg.sv)                                | Shift register for arbitrary types                                                                        | active       |                                     |
-| [`shift_reg_gated`](src/shift_reg_gated.sv)                    | Shift register with ICG for arbitrary types                                                               | active       |                                     |
+| [`shift_register`](src/shift_register.sv)                      | Shift register for arbitrary types                                                                        | active       |                                     |
+| [`shift_register_gated`](src/shift_register_gated.sv)          | Shift register with ICG for arbitrary types                                                               | active       |                                     |
 | [`rr_arb_tree`](src/rr_arb_tree.sv)                            | Round-robin arbiter for req/gnt and vld/rdy interfaces with optional priority                             | active       |                                     |
 | [`fall_through_register`](src/fall_through_register.sv)        | Fall-through register with ready/valid interface                                                          | active       |                                     |
 | [`spill_register_flushable`](src/spill_register_flushable.sv)  | Register with ready/valid interface to cut all combinational interface paths and additional flush signal. | active       |                                     |

common_cells.core

@@ -36,8 +36,8 @@ filesets:
       - src/cc_rr_arb_tree.sv
       - src/cc_rstgen_bypass.sv
       - src/cc_serial_deglitch.sv
-      - src/cc_shift_reg.sv
-      - src/cc_shift_reg_gated.sv
+      - src/cc_shift_register.sv
+      - src/cc_shift_register_gated.sv
       - src/cc_spill_register_flushable.sv
       - src/cc_stream_demux.sv
       - src/cc_stream_filter.sv

src/cc_shift_reg.sv → src/cc_shift_register.sv

@@ -13,7 +13,7 @@
 //
 // Description: Simple shift register for arbitrary depth and types
 
-module cc_shift_reg #(
+module cc_shift_register #(
     parameter type dtype         = logic,
     parameter int unsigned Depth = 1
 )(
@@ -23,10 +23,10 @@ module cc_shift_reg #(
     output dtype d_o
 );
 
-    cc_shift_reg_gated #(
+    cc_shift_register_gated #(
         .Depth(Depth),
         .dtype(dtype)
-    ) i_shift_reg_gated (
+    ) i_shift_register_gated (
         .clk_i  (clk_i),
         .rst_ni (rst_ni),
         .valid_i(1'b1),

src/cc_shift_reg_gated.sv → src/cc_shift_register_gated.sv

@@ -12,7 +12,7 @@
 
 `include "common_cells/registers.svh"
 
-module cc_shift_reg_gated #(
+module cc_shift_register_gated #(
   parameter int unsigned Depth = 32'd8,
   parameter type         dtype = logic
 ) (
@@ -32,7 +32,7 @@ module cc_shift_reg_gated #(
     assign data_o  = data_i;
 
   // It's a shift register if depth is greater than 0
-  end else begin : gen_shift_reg
+  end else begin : gen_shift_register
 
     logic [Depth-1 : 0] valid_d, valid_q;
     dtype [Depth-1 : 0] data_d, data_q;

src_files.yml

@@ -31,8 +31,8 @@ common_cells_all:
     - src/cc_rr_arb_tree.sv
     - src/cc_rstgen_bypass.sv
     - src/cc_serial_deglitch.sv
-    - src/cc_shift_reg.sv
-    - src/cc_shift_reg_gated.sv
+    - src/cc_shift_register.sv
+    - src/cc_shift_register_gated.sv
     - src/cc_spill_register_flushable.sv
     - src/cc_stream_demux.sv
     - src/cc_stream_filter.sv