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2 changes: 1 addition & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
/Bender.lock
/Bender.local
build
formal/fifo_v3
formal/fifo
formal/counter
formal/fall_through_register
*.check
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4 changes: 2 additions & 2 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ sources:
- src/cc_delta_counter.sv
- src/cc_edge_propagator_tx.sv
- src/cc_exp_backoff.sv
- src/cc_fifo_v3.sv
- src/cc_fifo.sv
- src/cc_gray_to_binary.sv
- src/cc_heaviside.sv
- src/cc_isochronous_4phase_handshake.sv
Expand Down Expand Up @@ -132,10 +132,10 @@ sources:
- test/cc_passthrough_stream_fifo_tb.sv
- test/cc_popcount_tb.sv
- test/cc_rr_arb_tree_tb.sv
- test/cc_test_pkg.sv
- test/cc_stream_register_tb.sv
- test/cc_stream_to_mem_tb.sv
- test/cc_sub_per_hash_tb.sv
- test/cc_test_pkg.sv
# Level 1
- test/cc_isochronous_crossing_tb.sv
- test/cc_stream_omega_net_tb.sv
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2 changes: 1 addition & 1 deletion README.md
Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ Please note that cells with status *deprecated* are not to be used for new desig
| Name | Description | Status | Superseded By |
| ---------------------------------------------------------------- | --------------------------------------------------------------------------- | ------------ | ----------------------------------------------------------------------------------------------- |
| [`cb_filter`](src/cb_filter.sv) | Counting-Bloom-Filter with combinational lookup | active | |
| [`fifo_v3`](src/fifo_v3.sv) | FIFO register with generic fill counts | active | |
| [`fifo`](src/fifo.sv) | FIFO register with generic fill counts | active | |
| [`passthrough_stream_fifo`](src/passthrough_stream_fifo.sv) | FIFO register with ready/valid interface and same-cycle push/pop when full | active | |
| [`ring_buffer`](src/ring_buffer.sv) | Ring buffer with sequential write and random-access read interfaces | active | |
| [`stream_fifo`](src/stream_fifo.sv) | FIFO register with ready/valid interface | active | |
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2 changes: 1 addition & 1 deletion common_cells.core
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ filesets:
- src/cc_delta_counter.sv
- src/cc_edge_propagator_tx.sv
- src/cc_exp_backoff.sv
- src/cc_fifo_v3.sv
- src/cc_fifo.sv
- src/cc_gray_to_binary.sv
- src/cc_isochronous_4phase_handshake.sv
- src/cc_isochronous_spill_register.sv
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8 changes: 4 additions & 4 deletions formal/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,9 @@ YOSYS ?= yosys
SBY ?= sby
RM ?= rm

all: fifo_v3.check counter.check fall_through_register.check
all: fifo.check counter.check fall_through_register.check

fifo_v3.check: fifo_v3.sby ../src/cc_fifo_v3.sv cc_fifo_v3_properties.sv
fifo.check: fifo.sby ../src/cc_fifo.sv cc_fifo_properties.sv
$(SBY) -f $<
touch $@

Expand All @@ -30,13 +30,13 @@ counter.check: counter.sby ../src/cc_counter.sv ../src/cc_delta_counter.sv cc_co
touch $@

fall_through_register.check: fall_through_register.sby ../src/cc_fall_through_register.sv \
../src/cc_fifo_v3.sv
../src/cc_fifo.sv
$(SBY) -f $<
touch $@

.PHONY: clean
clean:
$(RM) -r fifo_v3.check fifo_v3/
$(RM) -r fifo.check fifo/
# $(RM) -r delta_counter.check delta_counter/
$(RM) -r counter.check counter/
$(RM) -r fall_through_register.check fall_through_register/
12 changes: 6 additions & 6 deletions formal/cc_fifo_v3_properties.sv
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@

// Author: Robert Balas <balasr@iis.ee.ethz.ch>

module cc_fifo_v3_properties #(
module cc_fifo_properties #(
parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
Expand Down Expand Up @@ -40,7 +40,7 @@ module cc_fifo_v3_properties #(
);

localparam int unsigned FIFO_DEPTH = (DEPTH > 0) ? DEPTH : 1;
// verbatim from cc_fifo_v3
// verbatim from cc_fifo
localparam int unsigned FIFO_SIZE = FIFO_DEPTH[ADDR_DEPTH:0];

logic [ADDR_DEPTH-1:0] fill_level;
Expand Down Expand Up @@ -127,9 +127,9 @@ module cc_fifo_v3_properties #(
cover property (@(posedge clk_i)
empty_o == 1'b1);

endmodule // cc_fifo_v3_properties
endmodule // cc_fifo_properties

// propagate parameters from cc_fifo_v3 to properties
bind cc_fifo_v3 cc_fifo_v3_properties #(
// propagate parameters from cc_fifo to properties
bind cc_fifo cc_fifo_properties #(
.FALL_THROUGH(FALL_THROUGH), .DATA_WIDTH(DATA_WIDTH), .DEPTH(DEPTH)
) i_fifo_v3_properties(.*);
) i_fifo_properties(.*);
4 changes: 2 additions & 2 deletions formal/fall_through_register.sby
Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,12 @@ depth 100
smtbmc

[script]
read -formal cc_fifo_v3.sv
read -formal cc_fifo.sv
read -formal cc_fall_through_register.sv
read -formal cc_fall_through_register_properties.sv
prep -top cc_fall_through_register

[files]
cc_fall_through_register_properties.sv
../src/cc_fall_through_register.sv
../src/cc_fifo_v3.sv
../src/cc_fifo.sv
10 changes: 5 additions & 5 deletions formal/fifo_v3.sby
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ depth 100
smtbmc

[script]
read -formal cc_fifo_v3.sv
read -formal cc_fifo_v3_properties.sv
prep -top cc_fifo_v3
read -formal cc_fifo.sv
read -formal cc_fifo_properties.sv
prep -top cc_fifo

[files]
cc_fifo_v3_properties.sv
../src/cc_fifo_v3.sv
cc_fifo_properties.sv
../src/cc_fifo.sv
2 changes: 1 addition & 1 deletion src/cc_fall_through_register.sv
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ module cc_fall_through_register #(
logic fifo_empty,
fifo_full;

cc_fifo_v3 #(
cc_fifo #(
.FALL_THROUGH (1'b1),
.DEPTH (1),
.dtype (T)
Expand Down
4 changes: 2 additions & 2 deletions src/cc_fifo_v3.sv → src/cc_fifo.sv
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@

`include "common_cells/assertions.svh"

module cc_fifo_v3 #(
module cc_fifo #(
parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
Expand Down Expand Up @@ -148,4 +148,4 @@ module cc_fifo_v3 #(
"Trying to pop data although the FIFO is empty.")
`endif

endmodule // cc_fifo_v3
endmodule // cc_fifo
2 changes: 1 addition & 1 deletion src/cc_mem_to_banks_detailed.sv
Original file line number Diff line number Diff line change
Expand Up @@ -171,7 +171,7 @@ module cc_mem_to_banks_detailed #(
assign gnt_o = (&req_ready) & (&resp_ready) & !dead_write_fifo_full;

if (HideStrb) begin : gen_dead_write_fifo
cc_fifo_v3 #(
cc_fifo #(
.FALL_THROUGH ( 1'b0 ),
.DEPTH ( MaxTrans+1 ),
.DATA_WIDTH ( NumBanks )
Expand Down
2 changes: 1 addition & 1 deletion src/cc_stream_fifo.sv
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ module cc_stream_fifo #(
assign ready_o = ~full;
assign valid_o = ~empty;

cc_fifo_v3 #(
cc_fifo #(
.FALL_THROUGH (FALL_THROUGH),
.DATA_WIDTH (DATA_WIDTH),
.DEPTH (DEPTH),
Expand Down
2 changes: 1 addition & 1 deletion src_files.yml
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ common_cells_all:
- src/cc_delta_counter.sv
- src/cc_edge_propagator_tx.sv
- src/cc_exp_backoff.sv
- src/cc_fifo_v3.sv
- src/cc_fifo.sv
- src/cc_gray_to_binary.sv
- src/cc_heaviside.sv
- src/cc_isochronous_4phase_handshake.sv
Expand Down
2 changes: 1 addition & 1 deletion test/cc_fifo_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ module cc_fifo_inst_tb #(

assign clk = clk_i;

cc_fifo_v3 #(
cc_fifo #(
.FALL_THROUGH ( FALL_THROUGH ),
.DATA_WIDTH ( DATA_WIDTH ),
.DEPTH ( DEPTH )
Expand Down
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