eth: A proposal to add Ethernet interface & RGMII transceiver module#5
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ghost wants to merge 5 commits intom-labs:masterfrom
Open
eth: A proposal to add Ethernet interface & RGMII transceiver module#5ghost wants to merge 5 commits intom-labs:masterfrom
ghost wants to merge 5 commits intom-labs:masterfrom
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On this pull request, I propose a fundamental design for implementing the Ethernet interface and a working RGMII transmitter/receiver module. Here are the main features:
eth.Endpoint: A representation of a container for the received/transmitted packet. It is based on MiSoC'sstream.Endpointand LiteEthMini. This Python module can be used and further extended for implementing the MAC interface, such the Preamble and CRC.eth.rgmii.EthRGMII: A RGMII transmitter/receiver module. Separately,EthRGMIITXandEthRGMIIRXare the transmitter and receiver module respectively. Currently, no unit tests were made, but the modules have been tested on a Lattice ECP5, using these two SoC module designs: