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This repository was archived by the owner on Jan 5, 2026. It is now read-only.

Pull requests: m-labs/migen

11 Open 167 Closed
11 Open 167 Closed
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Pull requests list

feature: Add RoundRobin SP_TIMESLICE switch policy
#314 opened Aug 5, 2025 by thiagomoraisee Loading…
4 tasks done
toolchain: Add IOB attribute
#310 opened May 21, 2025 by occheung Contributor Loading…
Improve slice handling in _Value class to return self for specific cases
#299 opened Jan 13, 2025 by maass-hamburg Contributor Loading…
2
Fix ECP5 BRAM packing
#262 opened Jul 7, 2022 by madscientist159 Loading…
9
[WIP] coraz7: fix _connectors
#232 opened Dec 24, 2020 by astro Contributor Loading…
[enh] use Misc() properties in trellis' PCF
#221 opened Oct 4, 2020 by chmousset Loading…
1
examples/sim: add shift(-right) register examples
#217 opened Aug 27, 2020 by HarryMakes Contributor • Draft
2
migen.fhdl.specials: add per bit oe option to TSTriple
#205 opened Feb 26, 2020 by TomKeddie Loading…
2
migen.genlib: Improve "first word fall through" docs.
#152 opened Oct 27, 2018 by mithro Contributor Loading…
4
Ensure Memory that has a port with async_read=True is actually implemented as distributed ram
#105 opened Mar 29, 2018 by nakengelhardt Contributor Loading…
Output better error message for flash_proxy.
#79 opened Oct 8, 2017 by mithro Contributor Loading…
3
ProTip! Updated in the last three days: updated:>2026-04-21.