Debug Module ongoing integration into Mocha#436
Debug Module ongoing integration into Mocha#436alexandrecapltd wants to merge 2 commits intolowRISC:wip-riscv-dbg-integratefrom
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marnovandermaas
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marnovandermaas
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Good initial go at this. It would make it easier to review if you split this PR up into some separate commits. It would also be good if you could add some comments on how to test the code changes.
I've added some initial comments. It's probably worth rebasing to include the power and reset managers.
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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Nit: introduce an extra newline
| // Debug module master interface signals | ||
| logic dm_master_req; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_master_add; | ||
| logic dm_master_we; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_master_wdata; | ||
| logic [CVA6Cfg.XLEN/8-1:0] dm_master_be; | ||
| logic dm_master_gnt; | ||
| logic dm_master_r_valid; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_master_r_rdata; | ||
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| // Debug module slave interface signals | ||
| logic dm_slave_req; | ||
| logic dm_slave_we; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_slave_addr; | ||
| logic [CVA6Cfg.XLEN/8-1:0] dm_slave_be; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_slave_wdata; | ||
| logic [CVA6Cfg.XLEN-1:0] dm_slave_rdata; |
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Please use manager and subordinate in sources that are not vendored in.
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This'll need to be redone because I've integrated the reset manager. You should be able to pass this into the power manager like we do in Earl Grey: https://github.com/lowRISC/opentitan/blob/a1571d0a9873b15b218405ef368a0f89fecd06e9/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv#L1886
| //`AXI_ASSIGN_FROM_REQ(axi_debug_master, xbar_device_req[top_pkg::DM_DEV]) | ||
| //`AXI_ASSIGN_TO_RESP(xbar_device_resp[top_pkg::DM_DEV], axi_debug_master) | ||
| //axi2mem #( | ||
| // .AXI_ID_WIDTH ( top_pkg::AxiIdWidth ), | ||
| // .AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ), | ||
| // .AXI_DATA_WIDTH ( CVA6Cfg.XLEN ), | ||
| // .AXI_USER_WIDTH ( top_pkg::AxiUserWidth ) | ||
| //) i_dm_axi2mem ( | ||
| // .clk_i ( clk_i ), | ||
| // .rst_ni ( rst_ni ), | ||
| // .slave ( axi_debug_master ), | ||
| // .req_o ( dm_slave_req ), | ||
| // .we_o ( dm_slave_we ), | ||
| // .addr_o ( dm_slave_addr ), | ||
| // .be_o ( dm_slave_be ), | ||
| // .data_o ( dm_slave_wdata ), | ||
| // .data_i ( dm_slave_rdata ), | ||
| // .user_o ( '0 ), | ||
| // .user_i ( '0 ) | ||
| //); |
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Nit: remove commented code.
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Debug module is at 0x2000_0000, see https://github.com/lowRISC/mocha/blob/main/doc/ref/arch.md
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Is this because of the extra host?
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Very nice, I should do this for the other vendored core files as well.
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This vendor file should also be added to artefacts.py so we can check it in CI.
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In terms of which debug module to pull in, I think this should be the same as the one you are using for debugging in the CapLtd CVA6 repository. |
…00000 to 0x20000000 and propagate the change into top_chip
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This PR captures ongoing work to integrate the riscv-dbg module into mocha, following up on #303.
Currently,
jtagdpiandtcp_serveripsjtagdpiinstance has been added tohw/top_chip/dv/verilator/top_chip_verilator.svand connected thetop_chip_systemmodule jtag pins.hw/top_chip/rtl/top_chip_system.svnow has a debug module instance connected through converter modules (dmi_jtagfor the debug module interface,axi_adapterfor the master interface andaxi_to_memfor the slave interface). The jtag pins are exported. Thedebug_req_irqis connected to the CVA6 core, and the reset coming out of the debug module is in use (ndmreset_n = (~ndmreset) & rst_ni).hw/top_chip/rtl/top_pkg.sv, the SoC configuration accounts for the added debug module.This now builds for me, so I open this PR for others to be able to take a look.
I lifted the earlgrey openocd configuration from the opentitan repository. When simulating and trying to attach, the generated traces show traffic on the jtag interface, as well as a debug irq eventually being triggered. The CVA6 core which was emitting traffic on its noc_req signals goes silent, and openocd reports that the core failed to halt.
Things to investigate: