[hw] rom_ctrl added to mocha

hw/top_chip/chip_mocha_genesys2.core

@@ -40,6 +40,12 @@ parameters:
     default: ""
     paramtype: vlogparam
 
+  RomInitFile:
+    datatype: str
+    description: ROM initialization file in 32 bit vmem hex format
+    default: ""
+    paramtype: vlogparam
+
 targets:
   default: &default_target
     filesets:
@@ -54,6 +60,7 @@ targets:
     toplevel: chip_mocha_genesys2
     parameters:
       - BootRomInitFile
+      - RomInitFile
     tools:
       vivado:
         part: "xc7k325tffg900-2" # Genesys 2 with K325T

hw/top_chip/dv/env/top_chip_dv_env_pkg.sv

@@ -15,7 +15,8 @@ package top_chip_dv_env_pkg;
   `include "dv_macros.svh"
 
   typedef enum {
-    ChipMemSRAM
+    ChipMemSRAM,
+    ChipMemROM
   } chip_mem_e;
 
   typedef chip_mem_e chip_mem_list_t[$];

hw/top_chip/dv/tb/chip_hier_macros.svh

@@ -7,6 +7,7 @@
 `define CPU_HIER `SYSTEM_HIER.i_cva6
 `define SRAM_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_ram.mem
 `define TAG_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_tag_ram.mem
+`define ROM_MEM_HIER `SYSTEM_HIER.u_rom_ctrl.gen_rom_scramble_disabled.u_rom.u_prim_rom.mem
 
 // Testbench related
 `define SIM_SRAM_IF u_sim_sram.u_sim_sram_if

hw/top_chip/dv/tb/tb.sv

@@ -48,7 +48,10 @@ module tb;
   );
 
   // ------ DUT ------
-  top_chip_system #() dut (
+  top_chip_system #(
+    .SramInitFile(""),
+    .RomInitFile("")
+  ) dut (
     // Clock and reset.
     .clk_i                (clk              ),
     .rst_ni               (rst_n            ),
@@ -136,6 +139,18 @@ module tb;
       m_mem_bkdr_util[ChipMemSRAM].clear_mem();
       `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemSRAM], `SRAM_MEM_HIER)
 
+      m_mem_bkdr_util[ChipMemROM] = new(
+        .name                 ("mem_bkdr_util[ChipMemROM]"        ),
+        .path                 (`DV_STRINGIFY(`ROM_MEM_HIER)        ),
+        .depth                ($size(`ROM_MEM_HIER)                ),
+        .n_bits               ($bits(`ROM_MEM_HIER)                ),
+        .err_detection_scheme (mem_bkdr_util_pkg::ErrDetectionNone),
+        .system_base_addr     (top_pkg::RomCtrlMemBase             )
+      );
+
+      `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemROM], `ROM_MEM_HIER)
+
+
       // TODO MVy, see if required
       // Zero-initialise the SRAM Capability tags, otherwise TL-UL FIFO assertions will fire;
       // mem_bkdr_util does not handle the geometry of this memory.

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -150,7 +150,22 @@
       name: rom_ctrl_integrity_check
       uvm_test_seq: top_chip_dv_rom_ctrl_integrity_check_vseq
       sw_images: ["rom_ctrl_integrity_check_test_vanilla_bare:5"]
-      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_integrity_check_test_vanilla_bare.vmem"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_integrity_check_test_vanilla_bare.vmem",
+                 "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"]
+    }
+    {
+      name: rom_ctrl_smoke
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["rom_ctrl_smoketest_vanilla_bare:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_smoketest_vanilla_bare.vmem",
+                 "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"]
+    }
+    {
+      name: rom_ctrl_smoke_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["rom_ctrl_smoketest_cheri_bare:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_smoketest_cheri_bare.vmem",
+                 "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"]
     }
     {
       name: rv_dm_ndm_reset_req
@@ -237,7 +252,7 @@
         "mailbox_smoke",
         "mailbox_smoke_cheri",
         "axi_sram_smoke",
-        "axi_sram_smoke_cheri",
+        "axi_sram_smoke_cheri"
       ]
     }
     {
@@ -293,7 +308,8 @@
     {
       name: rom_ctrl
       tests: [
-        "rom_ctrl_integrity_check"
+        "rom_ctrl_integrity_check",
+        "rom_ctrl_smoke"
       ]
     }
     {

hw/top_chip/dv/verilator/top_chip_verilator.cc

@@ -21,7 +21,7 @@ class MochaSim {
  protected:
   top_chip_verilator _top;
   VerilatorMemUtil _memutil;
-  MemArea _sram, _dram;
+  MemArea _sram, _dram, _rom;
 
   virtual int Setup(int argc, char **argv, bool &exit_app);
   virtual void Run();
@@ -31,7 +31,8 @@ class MochaSim {
 MochaSim::MochaSim(const char *sram_hier_path, int sram_size_words,
                    const char *dram_hier_path, int dram_size_words)
     : _sram(sram_hier_path, sram_size_words, 8),
-      _dram(dram_hier_path, dram_size_words, 8) {}
+      _dram(dram_hier_path, dram_size_words, 8),
+      _rom("TOP.top_chip_verilator.u_top_chip_system.u_rom_ctrl.gen_rom_scramble_disabled.u_rom.u_prim_rom", 8192, 4) {}
 
 int MochaSim::Main(int argc, char **argv) {
   bool exit_app;
@@ -58,6 +59,7 @@ int MochaSim::Setup(int argc, char **argv, bool &exit_app) {
 
   _memutil.RegisterMemoryArea("sram", 0x10000000, &_sram);
   _memutil.RegisterMemoryArea("dram", 0x80000000, &_dram);
+  _memutil.RegisterMemoryArea("rom", 0x00080000, &_rom);
   simctrl.RegisterExtension(&_memutil);
 
   exit_app = false;

hw/top_chip/dv/verilator/top_chip_verilator.sv

@@ -43,6 +43,8 @@ module top_chip_verilator (input logic clk_i, rst_ni);
 
   // CHERI Mocha top
   top_chip_system #(
+    .SramInitFile(""),
+    .RomInitFile("")
   ) u_top_chip_system (
     .clk_i,
     .rst_ni,

hw/top_chip/ip/xbar_peri/data/xbar_peri.hjson

@@ -71,6 +71,18 @@
         size_byte: "0x00010000",
       }],
     },
+    { name:  "rom_ctrl_regs", // Rom_ctrl_regs
+      type:  "device",
+      clock: "clk_main_i",
+      reset: "rst_main_ni",
+      xbar:  false,
+      addr_range: [{
+        base_addrs: {
+          hart: "0x40050000",
+        },
+        size_byte: "0x00010000",
+      }],
+    },
     { name:  "uart", // UART
       type:  "device",
       clock: "clk_io_i",
@@ -150,6 +162,7 @@
       "clkmgr",
       "rstmgr",
       "pwrmgr",
+      "rom_ctrl_regs",
       "uart",
       "i2c",
       "spi_device",
@@ -159,4 +172,3 @@
     ],
   },
 }
-