Strengthen Illegal Instruction Handling by Eliminating All Side Effects in Decoder + Testbench#2393
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This PR strengthens illegal instruction handling in the decoder by ensuring that
no unintended side effects occur when an illegal instruction is detected.
Enhancements include:
A SystemVerilog testbench is included to verify that all side effects are fully suppressed.
This improves decoder robustness and aligns behavior with safe pipeline design practices.