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karthikeyan-designs/README.md

👋 Hi there, I'm Karthikeyan!

I'm an aspiring Digital Design and FPGA Engineer focused on RTL design, FPGA-based systems, and VLSI circuit design. I enjoy building hardware–software co-design systems and exploring efficient implementations of real-time applications.

🔧 Areas of Interest

  • RTL Design and FPGA Prototyping
  • HPS–FPGA SoC Systems
  • CMOS Circuit Design and SPICE Simulation
  • Open-source EDA Tools

🛠️ Tools & Technologies

  • Verilog
  • Quartus Prime
  • Platform Designer
  • Cadence Virtuoso
  • eSim
  • NGSpice
  • Magic VLSI
  • SKY130 PDK
  • OpenLANE

🚀 Key Skills Demonstrated

  • FPGA-based hardware acceleration (Verilog)
  • HPS–FPGA co-design (Cyclone V SoC)
  • Memory-mapped AXI interfacing using PIO
  • Image processing (Sobel edge detection)

⚡ Let's wire ideas into silicon!

Profile Views

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  1. fpga-solar-panel-fault-detection fpga-solar-panel-fault-detection Public

    FPGA | HPS co-design for real-time visual inspection of solar panels. Sobel edge detection in Verilog, defect classification in C on ARM Cortex-A9. DE1-SoC · Quartus Prime ·

    C

  2. soc-physical-design-openlane soc-physical-design-openlane Public

    This repository documents the complete RTL-to-GDSII physical design implementation of the picorv32a RISC-V processor core using open-source EDA tools. The project was completed as part of the Digit…

  3. Low-Power-Approximate-Adder-Design-and-Simulation-in-Cadence-Virtuoso-180nm-Technology- Low-Power-Approximate-Adder-Design-and-Simulation-in-Cadence-Virtuoso-180nm-Technology- Public

    Designed and simulated a low-power approximate adder using Cadence Virtuoso at 180nm CMOS

    1

  4. CMOS-Circuit-Analysis-using-SKY130-PDK CMOS-Circuit-Analysis-using-SKY130-PDK Public

    CMOS digital circuit characterization (IV curves, transient analysis, delay, power, noise margin, pre-layout and post-layout) using SKY130 PDK with NgSpice, Xschem, and Magic.

  5. eSim eSim Public

    Forked from FOSSEE/eSim

    This repository contain source code for new flow of FreeEDA now know as eSim

    Python