A comprehensive, modular verification ecosystem designed for the AMBA AXI4 protocol. This repository contains high-performance UVM environments tailored for verifying AXI4 Master IPs, Slave IPs, and complete System-on-Chip (SoC) interconnects.
This suite is organized into modular directories to allow for component-level testing or full system-level integration.
- Status: ✅ Completed & Verified
- Purpose: A robust UVM environment used to verify AXI4 Slave targets (e.g., RAMs, peripherals).
- Target DUT: Alex Forencich AXI RAM.
- Highlights: Handshake saturation, 4KB boundary protection, and unaligned access testing.
- Status: 🏗️ Under Active Development
- Purpose: A UVM-based Slave VIP designed to verify AXI4 Master controllers.
- Current Focus: Implementing the Slave Driver handshake logic and internal memory model.
- Status: 📅 Roadmap
- Purpose: A unified VIP-to-VIP environment where the Master VIP and Slave VIP communicate directly. This will serve as the verification platform for a custom RISC-V Core interconnect integration.
- Phase 1: Complete and document the AXI4 Master VIP (Done).
- Phase 2: Develop the AXI4 Slave VIP with configurable response latencies (In Progress).
- Phase 3: Integrate components into a unified System VIP for interconnect verification.
- Phase 4: Deploy the suite to verify the AXI4 interface for the university lab's open-source RISC-V "Hornet" Core.
- Language: SystemVerilog 2012 / UVM 1.2
- Primary Simulator: Vivado XSim (Supported scripts included)
- Target Support: Future support planned for Cadence Xcellium.
The AXI RAM RTL used as the verification target for the Master VIP is provided by Alex Forencich.
This project is licensed under the MIT License. The UVM verification infrastructure, agents, and environments are provided for professional demonstration and educational purposes. See the LICENSE file for details.
Yusuf Tekin Hardware Design & Verification Engineer
