Add permute_1D_sparse_data Operation for Intel XPU#72
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Remove .gitkeep placeholders
- Add invert_permute kernel to CMake build - Implement invert_permute Python wrapper in ops.py - Register invert_permute operator with schema existence check - Add torch_library.h utility for schema validation
Add SYCL/XPU kernel implementation for invert_permute operation.
Add complete test coverage for invert_permute operator on XPU devices, covering correctness, validation, parity, and performance. Test coverage includes: - Correctness tests for int32/int64 with edge cases (empty, single element, identity, reverse, random permutations) - Input validation tests for invalid dimensions and dtypes - Meta function tests for torch.compile compatibility - PyTorch opcheck validation for operator conventions - Parametric tests with varying sizes (1 to 1M elements) - CPU-XPU parity tests to ensure consistent results - Performance benchmarks measuring execution time and bandwidth
- CMakeLists: add permute_1d_sparse_data.cpp to build sources - ops.py: add Python wrapper with type hints - ops_registry.cpp: register operator schema in fbgemm namespace
Implement SYCL/XPU kernel implementation of permute_1D_sparse_data operator for sparse jagged/1D format data permutation.
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Depends on #71
Add
permute_1D_sparse_dataOperation for Intel XPUThis PR introduces the
permute_1D_sparse_dataoperator to fbgemm-xpu, enabling permutation of sparse data in jagged/1D format on Intel XPU devices.Changes
Core Implementation
permute_1d_sparse_data.cpp/h): SYCL implementation with three specialized functors for permuting lengths, indices, and weighted data, plus optimized cumsum helpers for offset computationops_registry.cpp): Registers the operator with PyTorch's dispatch system using conditional schema registration to avoid conflictsops.py): Clean Python wrapper function with type hints supporting optional weights and length sum parametersInfrastructure
CMakeLists.txt): Added SYCL kernel to build configurationTesting
test_permute_1d_sparse_data.py):cc: @manuelhsantana, @flezaalv