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feat(aarch64): add WHP backend for ARM64 Windows #1638
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2ba9a0b
feat(aarch64): add WHP (Windows Hypervisor Platform) backend for ARM64
cshung 9b59799
fix: address cross-compilation issues for aarch64-pc-windows-msvc
cshung 1d3a299
fix(aarch64): make WHP backend operational
cshung 5cb75f1
fix(aarch64): correct GITS translator field name
cshung af8dafc
fix: gate architecture-specific vCPU reset
cshung 05d5350
fix(aarch64): address WHP review feedback
cshung c468267
fix(aarch64): harden WHP state handling
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -32,3 +32,5 @@ pub(crate) struct CommonDebugRegs { | |
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| #[cfg(kvm)] | ||
| pub(crate) mod kvm_reg; | ||
| #[cfg(windows)] | ||
| pub(crate) mod whp_reg; | ||
128 changes: 128 additions & 0 deletions
128
src/hyperlight_host/src/hypervisor/regs/aarch64/whp_reg.rs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,128 @@ | ||
| /* | ||
| Copyright 2026 The Hyperlight Authors. | ||
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| Licensed under the Apache License, Version 2.0 (the "License"); | ||
| you may not use this file except in compliance with the License. | ||
| You may obtain a copy of the License at | ||
|
|
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| http://www.apache.org/licenses/LICENSE-2.0 | ||
|
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| Unless required by applicable law or agreed to in writing, software | ||
| distributed under the License is distributed on an "AS IS" BASIS, | ||
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| See the License for the specific language governing permissions and | ||
| limitations under the License. | ||
| */ | ||
|
|
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| use windows::Win32::System::Hypervisor::WHV_REGISTER_NAME; | ||
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| const X0: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0002_0000); | ||
| const Q0: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0003_0000); | ||
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| pub(crate) const WHV_ARM64_REGISTER_PC: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0002_0022); | ||
| pub(crate) const WHV_ARM64_REGISTER_PSTATE: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0002_0023); | ||
| pub(crate) const WHV_ARM64_REGISTER_SP_EL0: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0002_0020); | ||
| pub(crate) const WHV_ARM64_REGISTER_SP_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0002_0021); | ||
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| pub(crate) const WHV_ARM64_REGISTER_SCTLR_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0002); | ||
| pub(crate) const WHV_ARM64_REGISTER_CPACR_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0004); | ||
| pub(crate) const WHV_ARM64_REGISTER_TTBR0_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0005); | ||
| pub(crate) const WHV_ARM64_REGISTER_TCR_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0007); | ||
| pub(crate) const WHV_ARM64_REGISTER_MAIR_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_000b); | ||
| pub(crate) const WHV_ARM64_REGISTER_VBAR_EL1: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_000c); | ||
| pub(crate) const WHV_ARM64_REGISTER_FPCR: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0012); | ||
| pub(crate) const WHV_ARM64_REGISTER_FPSR: WHV_REGISTER_NAME = WHV_REGISTER_NAME(0x0004_0013); | ||
|
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| pub(crate) const GP_REGISTER_NAMES: [WHV_REGISTER_NAME; 34] = [ | ||
| xreg(0), | ||
| xreg(1), | ||
| xreg(2), | ||
| xreg(3), | ||
| xreg(4), | ||
| xreg(5), | ||
| xreg(6), | ||
| xreg(7), | ||
| xreg(8), | ||
| xreg(9), | ||
| xreg(10), | ||
| xreg(11), | ||
| xreg(12), | ||
| xreg(13), | ||
| xreg(14), | ||
| xreg(15), | ||
| xreg(16), | ||
| xreg(17), | ||
| xreg(18), | ||
| xreg(19), | ||
| xreg(20), | ||
| xreg(21), | ||
| xreg(22), | ||
| xreg(23), | ||
| xreg(24), | ||
| xreg(25), | ||
| xreg(26), | ||
| xreg(27), | ||
| xreg(28), | ||
| xreg(29), | ||
| xreg(30), | ||
| WHV_ARM64_REGISTER_PC, | ||
| WHV_ARM64_REGISTER_SP_EL0, | ||
| WHV_ARM64_REGISTER_PSTATE, | ||
| ]; | ||
|
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| pub(crate) const FP_REGISTER_NAMES: [WHV_REGISTER_NAME; 34] = [ | ||
| qreg(0), | ||
| qreg(1), | ||
| qreg(2), | ||
| qreg(3), | ||
| qreg(4), | ||
| qreg(5), | ||
| qreg(6), | ||
| qreg(7), | ||
| qreg(8), | ||
| qreg(9), | ||
| qreg(10), | ||
| qreg(11), | ||
| qreg(12), | ||
| qreg(13), | ||
| qreg(14), | ||
| qreg(15), | ||
| qreg(16), | ||
| qreg(17), | ||
| qreg(18), | ||
| qreg(19), | ||
| qreg(20), | ||
| qreg(21), | ||
| qreg(22), | ||
| qreg(23), | ||
| qreg(24), | ||
| qreg(25), | ||
| qreg(26), | ||
| qreg(27), | ||
| qreg(28), | ||
| qreg(29), | ||
| qreg(30), | ||
| qreg(31), | ||
| WHV_ARM64_REGISTER_FPSR, | ||
| WHV_ARM64_REGISTER_FPCR, | ||
| ]; | ||
|
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| pub(crate) const SPECIAL_REGISTER_NAMES: [WHV_REGISTER_NAME; 7] = [ | ||
| WHV_ARM64_REGISTER_TTBR0_EL1, | ||
| WHV_ARM64_REGISTER_TCR_EL1, | ||
| WHV_ARM64_REGISTER_MAIR_EL1, | ||
| WHV_ARM64_REGISTER_SCTLR_EL1, | ||
| WHV_ARM64_REGISTER_CPACR_EL1, | ||
| WHV_ARM64_REGISTER_VBAR_EL1, | ||
| WHV_ARM64_REGISTER_SP_EL1, | ||
| ]; | ||
|
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| pub(crate) const fn xreg(index: u32) -> WHV_REGISTER_NAME { | ||
| assert!(index < 31); | ||
| WHV_REGISTER_NAME(X0.0 + index as i32) | ||
| } | ||
|
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| pub(crate) const fn qreg(index: u32) -> WHV_REGISTER_NAME { | ||
| assert!(index < 32); | ||
| WHV_REGISTER_NAME(Q0.0 + index as i32) | ||
| } |
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Just a heads up that there is a big refactor/simplification to the interrupt handle machinery in #1674 that you may want to take a look at.