GitHub - harshitv95/Pipelined-MultiStaged-Processor-Simulator-2: A simulator for an out-of-order pipelined Micro Processor (CPU), having Multiple Functional Units, supporting all common types of instructions, and functionalities like the Load-Store Queue (LSQ), ReOrder Buffer (ROB), and the Issue Queue (IQ), along with Register Renaming

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B00817400_proj2		B00817400_proj2
.gitignore		.gitignore
CAO_Project2_documentation.docx		CAO_Project2_documentation.docx

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A simulator for an out-of-order pipelined Micro Processor (CPU), having Multiple Functional Units, supporting all common types of instructions, and functionalities like the Load-Store Queue (LSQ), ReOrder Buffer (ROB), and the Issue Queue (IQ), along with Register Renaming