CRC / Copy offloading to Intel Data Streaming Accelerator#470
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Adds optional offload of Navy's data checksumming to Intel DSA (Data
Streaming Accelerator), using the DTO library.
On the write path, the value copy into the region buffer and its CRC are
fused into a single DSA
Memory Copy with CRC Generationdescriptor thatthe calling fiber/thread submits before yielding; on the read path, all
verification sites (lookup, reclaim, cleanup, reinsertion, random-alloc)
can verify on the accelerator. BigHash bucket checksums offload with the
bloom-filter rebuild as the overlap work. Note, we need to use CRC32C for
compatible CRC polynomial for DSA.
Also adds DTO transparent usage to cache insertions in cachebench.
We use navyChecksumOffload
(+checksumOffloadMinSize, default 4096) and aBUILD_WITH_DTO` cmake option, with a runtimeDSA-vs-CPU parity self-check at engine creation that falls back to
software on mismatch.
Benchmarks
BigCache production trace replay (12M ops, ~48KB avg objects,
BlockCache-only, fiber scheduler):
ucache_bench (DCPerf, hybrid DRAM+Navy, small objects): CPU
−2.9% (fibers) / +0.7% (thread pool), P99.9 −14% / −21%, equal QPS.
How to test