gpio: phytium: update phytium gpio controller driver support to 6.6.0.4 by xiaqian1486 · Pull Request #1750 · deepin-community/kernel

xiaqian1486 · 2026-05-19T03:03:50Z

This patches updates the support for phytium gpio controller driver.

Rebind parent chained handler after resuming from S4
Remove redundant enable_irq in chained handler setup
Add PCI and platform dependency

Recording immediately after playing music will result in the latter part of the recording have no sound. the reason as follows: Playback and recording share the same clock. After playback stops, the audio framework will shutdown clock after 5-second. if recording within this 5-second period, the recording clock will be turned off. Therefore, the CONTROL1 register should be modified so that playback and recording use different clocks. Signed-off-by: Cheng Yulai <chengyulai1490@phytium.com.cn> Signed-off-by: Zhou Zheng <zhouzheng2069@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

This driver is exclusively for the PHYTIUM platform and is not compatible with other SoCs. This restriction avoids compiling this driver on other platforms. Signed-off-by: Cheng Yulai <chengyulai1490@phytium.com.cn> Signed-off-by: Zhou Zheng <zhouzheng2069@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Add a controller status code for no initialzation error. Signed-off-by: Cheng Yulai <chengyulai1490@phytium.com.cn> Signed-off-by: Zhou Zheng <zhouzheng2069@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Initialize channels and share memory before sending command to prevent unknown errors. Signed-off-by: Cheng Yulai <chengyulai1490@phytium.com.cn> Signed-off-by: Zhou Zheng <zhouzheng2069@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

When executing the probe interface, the driver shound return actual error code instead of zero to avoid creating sound card successfully when hardware is not present. Signed-off-by: Dai Jingtao <daijingtao1503@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Add audio control node to disable/enable I2S and DMA function. The node is used for dp-i2s to control audio whether it should stop or continue. Such as changing resolution when playing. Signed-off-by: Li Bing <libing1969@phytium.com.cn> Signed-off-by: Dai Jingtao <daijingtao1503@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

This driver is exclusively for the PHYTIUM platform and is not compatible with other SoCs. This restriction prevents errors on unsupported platform. Signed-off-by: Li Bing <libing1969@phytium.com.cn> Signed-off-by: Dai Jingtao <daijingtao1503@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

The problem is that when the hardware card is not inserted, it causes sound card loading to fail due to undefined behavior from headphone detection. This detection is in the I2S driver's probe function, but I2S cannot detect whether a daughter card actually exists. Therefore, the codec's probe should execute first and return directly if not daughter card is found. Signed-off-by: Li Bing <libing1969@phytium.com.cn> Signed-off-by: Dai Jingtao <daijingtao1503@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

This patch provides three methods for reading cpu type for Phytium Socs, with priority from high to low as follows: - read socid by arm-smccc - read system register of SYS_AIDR_EL1 - read system register of MPIDR_EL1 Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Feng Jun <fengjun@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

This patch adjusts the machanism of obtaining the CPU type for Phytium Socs. It can directly return current CPU type when external interface calls the function. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Feng Jun <fengjun@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Modify the definition of PE220x CPU name from PHYTIUM_CPU_PART_FTC303 to PHYTIUM_CPU_PART_FTC310 to support initialization and features for the FTC310 processor. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

zhaoxin inclusion category: feature -------------------- This patch extends temperature monitoring support to include the new Zhaoxin KX-8000 FMS CPU family by: 1. Adding model 0x8b to the MSR register mapping condition, so it uses the same temperature critical and maximum MSR addresses (0x175b and 0x175a) as the existing 0x6b and 0x7b models. 2. Registering both CENTAUR and ZHAOXIN vendor variants of the 0x8b model in the CPU ID matching table to enable driver probe on these systems. Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com>

Let ghes_edac be the preferred driver to load on __ZX__ and _BYO_ systems by extending the platform detection list in ghes.c Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> Tested-by: Lyle Li <LyleLi@zhaoxin.com> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> [ rjw: Subject and changelog edits ] Link: https://patch.msgid.link/20260128025216.12564-1-TonyWWang-oc@zhaoxin.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: LeoLiu-oc <leoliu-oc@zhaoxin.com>

* Introduce socket‑aware pin definition macros for multi‑socket platforms * Split global pin table into per‑socket pin tables with UID soc_data * Use UID‑based probe to match multi‑socket instances * Dynamically acquire PMIO IO resource instead of hard‑coding address * Fix PMIO offset for multi‑socket compatibility Signed-off-by: LeoLiu-oc <leoliu-oc@zhaoxin.com>

Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

Currently, cper_print_pcie() only logs Uncorrectable Error Status, Mask and Severity registers along with the TLP header. If a correctable error is received immediately preceding or following an Uncorrectable Fatal Error, its information is lost since Correctable Error Status and Mask registers are not logged. As such, to avoid skipping any possible error information, Correctable Error Status and Mask registers should also be logged. Additionally, ensure that AER information is also available through cper_print_pcie() for Correctable and Uncorrectable Non-Fatal Errors. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Tested-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Avadhut Naik <avadhut.naik@amd.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: LeoLiu-oc <leoliu-oc@zhaoxin.com>

This adds the DEVFREQ driver for Phytium Net On Chip.It adjusts frequency for noc based on load bandwidth obtained from register. Signed-off-by: Li Jiayi <lijiayi1493@phytium.com.cn> Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

This adds the DEVFREQ driver for Phytium DDR Memory Unit.It adjusts frequency for dmu based on load bandwidth obtained from register. Signed-off-by: Li Jiayi <lijiayi1493@phytium.com.cn> Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

The patch fixed dmu/noc devfreq driver some memory leak problem. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

The patch retrieves the base address from the ACPI table instead of being directly exposed inside the driver. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

This patch modifies and adds the following functions: 1). On account of DMU and DDR PMU drivers operate PMU registers at the same time, which will result in conflict. So the register operation of se in dmufreq is transferred to the upper driver. 2). The notification chain of dmufreq to DDR PMU is added in order to suspend dmufreq's register action and maintain the rate at the current frequency when the PMU driver is loaded. 3). Add suspend and resume features. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Change the default strategy for the DMU freq driver from simple demand to the performance mode. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Firstly, replace ioremap with devm_ioremap. The advantage of this approach is that it can be automatically managed during the unloading stage, eliminating the need for manual resource cleanup, thus preventing resource leakage. Secondly, resolve the repeated printing issues. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Delete the unnecessary release of resources when using devm_kzalloc function to allocate memory. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

This patch adds power mangement interface, Specifically adds the phytium_nocfreq_suspend/phytium_nocfreq_resume functions so that the frequency can be restored upon waking up. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Optimize the timer logic for sampling, with the aim of reducing the frequent calls made by processes within the system. It is very helpfull to reduce power consumption. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

uring driver probe, functions like get_freq_count() and phytium_noc_get_freq_info() call acpi_evaluate_object() with ACPI_ALLOCATE_BUFFER. This interface allocates memory via kmalloc to store the returned ACPI package, but the allocated buffer was never released after use. kmemleak reports unreferenced objects coming from acpi_ut_initialize_buffer() when probing the Phytium DMU freq drivers. Fix this by calling kfree(buffer.pointer) after the ACPI package has been parsed. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

During driver probe, functions like get_freq_count() and phytium_noc_get_freq_info() call acpi_evaluate_object() with ACPI_ALLOCATE_BUFFER. This interface allocates memory via kmalloc to store the returned ACPI package, but the allocated buffer was never released after use. kmemleak reports unreferenced objects coming from acpi_ut_initialize_buffer() when probing the Phytium NOC freq drivers. Fix this by calling kfree(buffer.pointer) after the ACPI package has been parsed. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Add DMU DEVFREQ driver Support for Phytium PS260xxx SoCs, and complatible with PD2408. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Add NOC DEVFREQ driver Support for Phytium PS260xxx SoCs, and complatible with PD2408. Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Ma Mingrui <mamingrui1243@phytium.com.cn>

Introduce driver support for the PCIe PMU v2p0. The driver enables discovery and registration of PMU capabilities in PCIe devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Introduce a unified driver support for the DDR performance monitoring unit. The driver enables discovery and registration of PMU capabilities in DDR devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Introduce driver support for the PCIe Link performance monitoring unit. The driver enables discovery and registration of PMU capabilities in PCIe Link devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Introduce driver support for the MSI performance monitoring unit. The driver enables discovery and registration of PMU capabilities in MSI devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Resolve the count error issue caused by acquiring event index error for DDR PMU drivers. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

When CONFIG_ARCH_PHYTIUM and CONFIG_ACPI are not set, but CONFIG_COMPILE_TEST is enabled, the pcie pmu driver fails to compile. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Modify the enable logic in PCIe Link PMU driver to properly set up time mode and start-stop mode. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Some PCI devices have IO space access limit and only supporting 16 bit addresses. We update upper 16 bits of I/O base/limit according to the bridge and the RC root port. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Xiao Cong <xiaocong1866@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

When the PCIe device is unplugged or under hotreset, the PCIe controller's protrction mechanism is triggered, which will make the link inaccessible. This patch disables the protection after the link is up and makes the PCIe hotplug or hotreset process work well. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Long Shixiang <longshixiang1718@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

The phytium PCIe root ports and X100 switch do not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Xiao Cong <xiaocong1866@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

In the phytium ps2308 platforms, when host PCIe bridge operate hotreset, then host pcie bridge config register will restore default value. So before hotreset, it need save host PCIe bridge config register. Then after hotreset, it need restore save host PCIe bridge config register. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Xiao Cong <xiaocong1866@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Some Phytium-based systems can come up with reduced PCIe link speed or lane count after a hotreset. A second reset attempt often restores the original link characteristics. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Li Tongfeng <litongfeng1497@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

On Phytium 24080 platform, reading the PCIe Link Status (LNKSTA) register through the standard PCIe capability interface may return an incorrect value for the Data Link Layer Link Active (DLLLA) bit. This causes the kernel to report wrong link state after a device is hot-unplugged. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Li Tongfeng <litongfeng1497@phytium.com.cn>

Add the device tree binding schema for phytium,pe2201-pcie-ep. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Li Tongfeng <litongfeng1497@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Add phytium ep driver DMA Controller support and add function_num_map to the configfs of EPC. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Li Tongfeng <litongfeng1497@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

On PD2308 platform, it only setup root bridge I/O BAR address, and don't modify other bridge I/O BAR address after root. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Li Wencheng <liwencheng@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

This reverts commit 6dd7290. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn>

Fix module (=m) case where GPIO interrupts stop after S4 resume because the parent IRQ loses the chained handler setting up at probe. So rebind the handler for each parent in resume() to restore parent-to-child dispatch. While builtin (=y) builds unaffected. Mainline: Open-Source Signed-off-by: zhuling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>

Linux PM framework automatically calls suspend_device_irqs() during suspend to disable IRQs, and resume_device_irqs() during resume to re-enable them. The current GPIO driver redundantly calls enable_irq() in its resume flow, which will create an unbalanced IRQ enable since the kernel has already restored the IRQ state through resume_device_irqs(). Mainline: Open-Source Signed-off-by: Zhu Ling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>

Ensure the Phytium GPIO PCI driver is only selectable for its intended environment. This driver depends on both the Phytium platform and a working PCI subsystem. Mainline: Open-Source Signed-off-by: Zhu Ling <zhuling2709@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Xia Qian <xiaqian1486@phytium.com.cn>

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deepin-ci-robot · 2026-05-19T03:03:58Z

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deepin-ci-robot · 2026-05-19T03:04:18Z

Hi @xiaqian1486. Thanks for your PR.

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Pull request overview

This PR updates and extends Phytium (and related Zhaoxin) platform support against the 6.6.0.4 kernel baseline, spanning GPIO suspend/resume handling as well as several adjacent subsystems (ASoC, PCI endpoint/hotplug, perf PMUs, devfreq, DT bindings, and maintenance metadata).

Changes:

GPIO: rebind chained parent IRQ handler after S4 resume and related driver adjustments.
Audio: improve ASoC machine/DP link identification and error handling; add new sysfs control; update Phytium codec handling and ES8388 init.
PCI/perf/devfreq/platform: add Phytium-specific PCI EPC DMA hooks + DT binding/MAINTAINERS updates; extend HDA handling for Zhaoxin; add/update Phytium perf PMUs and devfreq drivers; various cleanups/guards (e.g., XFS trace compat guard).

Reviewed changes

Copilot reviewed 52 out of 52 changed files in this pull request and generated 21 comments.

Show a summary per file

File	Description
sound/soc/phytium/pmdk_dp.c	Propagates jack setup return value; assigns DAI link IDs for DP audio links.
sound/soc/phytium/phytium-machine-v2.c	Adds DAI link ID for the V2 machine link.
sound/soc/phytium/phytium-i2s-v2.c	Updates version; sets component options; adds sysfs control attribute.
sound/soc/phytium/Kconfig	Adds ARCH_PHYTIUM dependency and formats help text consistently.
sound/soc/codecs/phytium-codec-v2.h	Introduces a codec status enum for clearer error reporting.
sound/soc/codecs/phytium-codec-v2.c	Reworks status handling; clears shared command structure at key transitions; stores channel count in priv.
sound/soc/codecs/Kconfig	Adds ARCH_PHYTIUM dependency for Phytium codec v2.
sound/soc/codecs/es8388.c	Updates version and adds error handling during component probe initialization.
sound/pci/hda/patch_hdmi.c	Adds additional HDMI/DP codec IDs mapped to gf HDMI patch handler.
sound/pci/hda/hda_intel.c	Extends VIA-specific position fix / snoop behavior and adds new PCI IDs for Zhaoxin HDMI controllers.
drivers/gpio/gpio-phytium-platform.c	Rebinds chained handler on resume via helper; adjusts suspend/resume flow.
include/linux/pci-epc.h	Adds Phytium-specific EPC DMA ops and exported APIs under CONFIG_ARCH_PHYTIUM.
drivers/pci/endpoint/pci-epc-core.c	Implements/exports Phytium-specific EPC DMA entry points.
drivers/pci/endpoint/pci-ep-cfs.c	Adds configfs exposure related to EPC function mapping.
drivers/pci/controller/pcie-phytium-ep.c	Updates Phytium PCIe EP controller behavior (BAR/DMA related paths).
Documentation/devicetree/bindings/pci/phytium,pe2201-pcie-ep.yaml	Adds DT binding for a Phytium PCIe EP device.
drivers/pci/hotplug/pciehp_hpc.c	Adds Phytium-specific link-status override logic for hotplug.
drivers/devfreq/phytium_noc.c	Adds/updates Phytium NoC devfreq driver functionality and PM behavior.
drivers/devfreq/phytium_dmu.c	Adds/updates Phytium DMU devfreq driver (incl. SPDX tag).
drivers/perf/phytium/phytium_ddr_pmu.c	Adds Phytium DDR PMU driver for perf.
drivers/perf/phytium/phytium_msi_pmu.c	Adds Phytium MSI PMU driver for perf (counter handling/overflow paths).
drivers/perf/phytium/phytium_pcie_link_pmu.c	Adds Phytium PCIe link PMU driver for perf (event/counter reads).
drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.h	Adds a helper macro for socket-specific pin definitions.
drivers/pinctrl/zhaoxin/pinctrl-kh50000.c	Refactors KH50000 pin definitions using the new socket macro; adjusts resource/init paths.
fs/xfs/xfs_trace.h	Adjusts tracepoint definitions/guards (e.g., compat-ioctl tracepoint under CONFIG_COMPAT).
MAINTAINERS	Extends Phytium maintainer file globs to cover additional bindings and drivers.

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+	p = kmalloc(size, GFP_KERNEL);
+	if (p == NULL)
+		return -EINVAL;
+	strscpy(p, buf, sizeof(p));
+


+	token = strsep(&p, " ");
+	if (!token) {
+		ret = -EINVAL;
+		goto error;
+	}
+
+	ret = kstrtol(token, 0, &value);
+	if (ret)
+		goto error;
+	loc = (u8)value;
+
+	if (loc == 1) {
+		//Enable I2S and DMA
+		phyt_writel_reg(priv->dma_reg_base, PHYTIUM_DMA_CTL, 1);
+		phyt_writel_reg(priv->regfile_base, PHYTIUM_REGFILE_ITER, TX_EN);
+	} else if (loc == 0) {
+		//Disable I2S and DMA
+		phyt_writel_reg(priv->regfile_base, PHYTIUM_REGFILE_ITER, TX_DIS);
+		phyt_writel_reg(priv->dma_reg_base, PHYTIUM_DMA_CTL, 0);
+	}
+
+	kfree(p);
+	return size;
+error:
+	kfree(p);
+	return ret;


 struct device;
 struct zhaoxin_pinctrl;

+#define SOCKET_PINCTRL_PIN(sock, a, b) PINCTRL_PIN(a, b"_"#sock)


+	res_pmio = platform_get_resource(pdev, IORESOURCE_IO, 0);
+	if (!res_pmio) {
+		dev_err(&pdev->dev, "can't fetch device pmio resource info\n");
+		return;
+	}
+
+	if (!request_region(res_pmio->start, resource_size(res_pmio), pdev->name)) {
+		dev_err(&pdev->dev, "can't request region\n");
+		return;
+	}


+	if (IS_ERR(epc))
+		return -EINVAL;
+
+	if (!epc->ops->start_dma)
+		return 0;


+		j = event_type * 5;
+		for (i = 0; i < 4; i++) {
+			reqid_val = readl(misc_pmu->base + misc_reqid_record_reg_offset[j]);
+			req_cnt = readl(misc_pmu->base + misc_counter_reg_offset[j]);
+			record_mov_bits = (i % 2) * 16;
+			reqid[i] = (u32)(0xFFFF & (reqid_val >> record_mov_bits));
+			cnt_mov_bits = i * 4;
+			reqcnt[i] = (u32)(0xF & (req_cnt >> cnt_mov_bits));
+			dev_info(misc_pmu->dev, "reqid(%u),cnt=%u\n", reqid[i], reqcnt[i]);
+			j += 1;


+	if ((event->attr.config & PHYTIUM_MSI_PMU_EVENT_MASK) > PHYTIUM_MISC_MAX_COUNTERS)
+		return -EINVAL;
+
+	if (misc_pmu->on_cpu == -1)
+		return -EINVAL;
+


+static irqreturn_t phytium_msi_pmu_overflow_handler(int irq, void *dev_id)
+{
+	struct phytium_msi_pmu *misc_pmu = dev_id;
+	struct perf_event *event;
+	unsigned long now_state, stop_state;
+	int idx, event_type;
+	unsigned long dev_stop_mask, dev_mask;
+	unsigned long *used_mask = misc_pmu->pmu_events.used_mask;
+	u32 opt_val = 0;
+	int event_added = bitmap_weight(used_mask, PHYTIUM_MISC_MAX_COUNTERS);
+
+	// 0:pcu 1:pxu 2:peu
+	now_state = phytium_msi_pmu_get_now_status(misc_pmu);
+
+	if (!is_interrupt_state(now_state))
+		return IRQ_NONE;
+
+	if (!event_added) {
+		phytium_msi_pmu_clear_counters(misc_pmu, MISC_MSI_MON_OPT_MASK);
+		return IRQ_HANDLED;
+	}
+
+	stop_state = phytium_msi_pmu_get_stop_status(misc_pmu);
+	if (stop_state & MISC_MSI_MON_COUNT_FULL_MASK) {
+		for_each_set_bit(idx, used_mask, PHYTIUM_MISC_MAX_COUNTERS) {
+			event = misc_pmu->pmu_events.hw_events[idx];
+			if (!event)
+				continue;
+			event_type = phytium_msi_pmu_get_event_type(event);
+			dev_stop_mask = pcie_dev_msi_mon_stop_mask[event_type];
+
+			if (stop_state & dev_stop_mask & MISC_MSI_MON_COUNT_FULL_MASK) {
+				phytium_msi_pmu_event_update(event);
+				opt_val |= pcie_dev_msi_mon_opt_bits[event_type];
+				set_bit(event_type, &dev_mask);
+			}


+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: reg
+      - const: mem
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+examples:
+  - |
+    ep0: ep@0x31000000 {
+      compatible = "phytium,pe2201-pcie-ep";
+      interrupts = <0x00000000 0x0000000a 0x00000004 0x00000000 0x0000000b 0x00000004>;
+      reg = <0x00000000 0x31000000 0x00000000 0x00010000 0x00000011 0x00000000 0x00000001 0x00000000 0x00000000 0x31100000 0x00000000 0x00001000>;
+      reg-names = "reg", "mem", "hpb";
+      max-outbound-regions = <0x00000003>;
+      max-functions = [02];


+/* Rebind parent-to-child dispatch chain and enable parent IRQ lines. */
+static void phytium_set_irq_chained_handler(struct phytium_gpio *gpio)
+{
+	struct gpio_irq_chip *girq = &gpio->gc.irq;
+	int i;


Chengyulai and others added 30 commits May 12, 2026 14:07

codec-v2: phytium: Add controller status code

f4648e6

Add a controller status code for no initialzation error. Signed-off-by: Cheng Yulai <chengyulai1490@phytium.com.cn> Signed-off-by: Zhou Zheng <zhouzheng2069@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

CI: arm64: disable debuginfo to speed up build test

3decc7d

Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

zhangfuxiang123 and others added 20 commits May 15, 2026 10:07

Revert "PCI: Add ACS quirk for phytium root and switch ports"

8209bf1

This reverts commit 6dd7290. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn>

sourcery-ai Bot reviewed May 19, 2026

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deepin-ci-robot requested review from justforlxz and myml May 19, 2026 03:03

deepin-ci-robot added the needs-ok-to-test label May 19, 2026

Avenger-285714 requested review from Avenger-285714 and Copilot May 19, 2026 05:04

Copilot started reviewing on behalf of Avenger-285714 May 19, 2026 05:07 View session

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gpio: phytium: update phytium gpio controller driver support to 6.6.0.4#1750

gpio: phytium: update phytium gpio controller driver support to 6.6.0.4#1750
xiaqian1486 wants to merge 82 commits into
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