qspi: phytium: update phytium qspi controller driver support to 6.6.0.4

.github/workflows/build-kernel-arm64.yml

@@ -30,10 +30,16 @@ jobs:
         run: |
           # .config
           make deepin_arm64_desktop_defconfig
+          scripts/config --enable CONFIG_DEBUG_INFO_NONE
+          scripts/config --disable CONFIG_DEBUG_INFO_DWARF5
+          make olddefconfig
           make -j$(nproc)
 
       - name: 'Clang build kernel'
         run: |
           # .config
           make LLVM=-18 deepin_arm64_desktop_defconfig
+          scripts/config --enable CONFIG_DEBUG_INFO_NONE
+          scripts/config --disable CONFIG_DEBUG_INFO_DWARF5
+          make LLVM=-18 olddefconfig
           make LLVM=-18 -j$(nproc)

Documentation/devicetree/bindings/pci/phytium,pe2201-pcie-ep.yaml

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/phytium,pe2201-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Phytium PCIe endpoint controller
+
+maintainers:
+  - Li Tongfeng <litongfeng1497@phytium.com.cn>
+
+allOf:
+  - $ref: "pci-ep.yaml#"
+
+properties:
+  compatible:
+    const: phytium,pe2201-pcie-ep
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: reg
+      - const: mem
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+examples:
+  - |
+    ep0: ep@0x31000000 {
+      compatible = "phytium,pe2201-pcie-ep";
+      interrupts = <0x00000000 0x0000000a 0x00000004 0x00000000 0x0000000b 0x00000004>;
+      reg = <0x00000000 0x31000000 0x00000000 0x00010000 0x00000011 0x00000000 0x00000001 0x00000000 0x00000000 0x31100000 0x00000000 0x00001000>;
+      reg-names = "reg", "mem", "hpb";
+      max-outbound-regions = <0x00000003>;
+      max-functions = [02];
+      status = "disabled";
+    };

MAINTAINERS

@@ -17547,10 +17547,15 @@ F:	Documentation/devicetree/bindings/gpio/phytium,gpio.yaml
 F:	Documentation/devicetree/bindings/usb/phytium,usb2-2.0.yaml
 F:	Documentation/devicetree/bindings/usb/phytium,usb2.yaml
 F:	Documentation/devicetree/bindings/usb/phytium.role-sw.yaml
+F:	Documentation/devicetree/bindings/pci/phytium,pe2201-pcie-ep.yaml
 F:	drivers/usb/phytium/*
+F:	drivers/perf/phytium/phytium_ddr_pmu.c
+F:	drivers/perf/phytium/phytium_msi_pmu.c
+F:	drivers/perf/phytium/phytium_pcie_link_pmu.c
 F:	drivers/usb/phytium/phytium_usb_v2*
 F:	drivers/usb/typec/role-switch-phytium.c
 F:	arch/arm64/boot/dts/phytium/*
+F:	arch/arm64/include/asm/phytium_cputype.h
 F:	drivers/gpio/gpio-phytium*
 
 QAT DRIVER

arch/arm64/configs/deepin_arm64_desktop_defconfig

@@ -4089,6 +4089,8 @@ CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
 CONFIG_DEVFREQ_GOV_PERFORMANCE=m
 CONFIG_DEVFREQ_GOV_POWERSAVE=m
 CONFIG_DEVFREQ_GOV_USERSPACE=m
+CONFIG_ARM_PHYTIUM_NOC_DEVFREQ=m
+CONFIG_ARM_PHYTIUM_DMU_DEVFREQ=m
 CONFIG_PM_DEVFREQ_EVENT=y
 CONFIG_EXTCON_GPIO=m
 CONFIG_EXTCON_MAX14577=m

arch/arm64/include/asm/cputype.h

@@ -156,7 +156,7 @@
 
 #define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */
 
-#define PHYTIUM_CPU_PART_FTC303		0x303
+#define PHYTIUM_CPU_PART_FTC310		0x303
 #define PHYTIUM_CPU_PART_FTC660		0x660
 #define PHYTIUM_CPU_PART_FTC661		0x661
 #define PHYTIUM_CPU_PART_FTC662		0x662
@@ -240,7 +240,7 @@
 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
 #define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
-#define MIDR_PHYTIUM_FTC303 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC303)
+#define MIDR_PHYTIUM_FTC310 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC310)
 #define MIDR_PHYTIUM_FTC660 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC660)
 #define MIDR_PHYTIUM_FTC661 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC661)
 #define MIDR_PHYTIUM_PS17064 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662)

arch/arm64/include/asm/phytium_cputype.h

@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025, Phytium Technology Co., Ltd.
+ */
+#ifndef __ASM_PHYTIUM_CPUTYPE_H
+#define __ASM_PHYTIUM_CPUTYPE_H
+
+#include <linux/arm-smccc.h>
+#include <asm/cputype.h>
+
+#define SOC_ID_PE1702	0x1
+#define SOC_ID_PS17064	0x2
+#define SOC_ID_PD1904	0x3
+#define SOC_ID_PS20064	0x4
+
+#define SOC_ID_PD2008	0x5
+#define SOC_ID_PS21064	0x6
+#define SOC_ID_PE220X	0x7
+#define SOC_ID_PS23064	0x8
+#define SOC_ID_PD2308	0x9
+#define SOC_ID_PS2480	0xa
+#define SOC_ID_PD2408	0xb
+
+#define SYS_REG_VAL_PS24080	0x6
+#define SYS_REG_VAL_PS23064	0x8
+
+#define SMCCC_SUCCESS		0
+#define SMCCC_FAILURE		(-1)
+#define FUNC_ID_GET_CPU_VERSION 0xc2000002
+
+enum phyt_soc_type {
+	PE1702 = 1,
+	PS17064,
+	PD1904,
+	PS20064,
+	PD2008,
+	PS21064,
+	PE220X,
+	PS23064,
+	PD2308,
+	PS24080,
+	PD2408,
+	PS15016,
+	UNKNOWN_SOC
+};
+
+extern enum phyt_soc_type phyt_soc_type_t;
+
+static enum phyt_soc_type do_smccc_res(struct arm_smccc_res res)
+{
+	unsigned long smc_cpu_ver = res.a1;
+
+	smc_cpu_ver = (smc_cpu_ver >> 8);
+	switch (smc_cpu_ver) {
+	case SOC_ID_PE1702:
+		return PE1702;
+	case SOC_ID_PS17064:
+		return PS17064;
+	case SOC_ID_PD1904:
+		return PD1904;
+	case SOC_ID_PS20064:
+		return PS20064;
+	case SOC_ID_PD2008:
+		return PD2008;
+	case SOC_ID_PS21064:
+		return PS21064;
+	case SOC_ID_PE220X:
+		return PE220X;
+	case SOC_ID_PS23064:
+		return PS23064;
+	case SOC_ID_PD2308:
+		return PD2308;
+	case SOC_ID_PS2480:
+		return PS24080;
+	case SOC_ID_PD2408:
+		return PD2408;
+	default:
+		return UNKNOWN_SOC;
+	}
+}
+
+static enum phyt_soc_type do_read_sysreg(void)
+{
+	u32 aidr_reg_val = read_sysreg(aidr_el1);
+
+	switch (aidr_reg_val) {
+	case SYS_REG_VAL_PS24080:
+		return PS24080;
+	case SYS_REG_VAL_PS23064:
+		return PS23064;
+	default:
+		return UNKNOWN_SOC;
+	}
+}
+
+static enum phyt_soc_type do_read_mpidr(void)
+{
+	u32 part_id = read_cpuid_part_number();
+
+	switch (part_id) {
+	case PHYTIUM_CPU_PART_FTC310:
+		return PE220X;
+	case PHYTIUM_CPU_PART_FTC660:
+		return PS15016;
+	case PHYTIUM_CPU_PART_FTC661:
+		return PE1702;
+	case PHYTIUM_CPU_PART_FTC662:
+		return PS17064;
+	case PHYTIUM_CPU_PART_FTC663:
+		return PD1904;
+	case PHYTIUM_CPU_PART_FTC862:
+		return PD2408;
+	default:
+		return UNKNOWN_SOC;
+	}
+}
+
+static inline bool is_phytium_soc(void)
+{
+	if (read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM)
+		return true;
+	return false;
+}
+
+static inline enum phyt_soc_type phyt_read_soc_type(void)
+{
+	enum phyt_soc_type ctype;
+	struct arm_smccc_res res;
+
+	if (!is_phytium_soc())
+		return UNKNOWN_SOC;
+
+	arm_smccc_smc(FUNC_ID_GET_CPU_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+	switch (res.a0) {
+	case SMCCC_SUCCESS:
+		ctype = do_smccc_res(res);
+		if (ctype != UNKNOWN_SOC)
+			break;
+		fallthrough;
+	case SMCCC_FAILURE:
+		ctype = do_read_sysreg();
+		if (ctype != UNKNOWN_SOC)
+			break;
+		fallthrough;
+	default:
+		ctype = do_read_mpidr();
+		break;
+	}
+	return ctype;
+}
+
+static inline void phyt_soc_type_init(void)
+{
+	enum phyt_soc_type ctype = phyt_read_soc_type();
+
+	switch (ctype) {
+	case PE1702:
+		phyt_soc_type_t = PE1702;
+		break;
+	case PS17064:
+		phyt_soc_type_t = PS17064;
+		break;
+	case PD1904:
+		phyt_soc_type_t = PD1904;
+		break;
+	case PS20064:
+		phyt_soc_type_t = PS20064;
+		break;
+	case PD2008:
+		phyt_soc_type_t = PD2008;
+		break;
+	case PS21064:
+		phyt_soc_type_t = PS21064;
+		break;
+	case PE220X:
+		phyt_soc_type_t = PE220X;
+		break;
+	case PS23064:
+		phyt_soc_type_t = PS23064;
+		break;
+	case PD2308:
+		phyt_soc_type_t = PD2308;
+		break;
+	case PS24080:
+		phyt_soc_type_t = PS24080;
+		break;
+	case PD2408:
+		phyt_soc_type_t = PD2408;
+		break;
+	case PS15016:
+		phyt_soc_type_t = PS15016;
+		break;
+	default:
+		phyt_soc_type_t = UNKNOWN_SOC;
+		break;
+	}
+}
+
+static inline bool is_pd2408(void)
+{
+
+	if (phyt_soc_type_t == PD2408)
+		return true;
+	return false;
+}
+
+static inline bool is_ps23064(void)
+{
+
+	if (phyt_soc_type_t == PS23064)
+		return true;
+	return false;
+}
+
+static inline bool is_ps24080(void)
+{
+
+	if (phyt_soc_type_t == PS24080)
+		return true;
+	return false;
+}
+
+static inline bool is_pd2308(void)
+{
+
+	if (phyt_soc_type_t == PD2308)
+		return true;
+	return false;
+}
+
+static inline bool is_pe220x(void)
+{
+
+	if (phyt_soc_type_t == PE220X)
+		return true;
+	return false;
+}
+
+#endif
+
+

arch/arm64/kernel/cpufeature.c

@@ -1722,7 +1722,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
-		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303),
+		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310),
 		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC660),
 		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC661),
 		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_PS17064),

arch/arm64/kernel/proton-pack.c

@@ -163,7 +163,7 @@ static enum mitigation_state spectre_v2_get_cpu_hw_mitigation_state(void)
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 		MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
 		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
-		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303),
+		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310),
 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
@@ -474,7 +474,7 @@ static enum mitigation_state spectre_v4_get_cpu_hw_mitigation_state(void)
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 		MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
-		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303),
+		MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310),
 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
 		{ /* sentinel */ },

arch/arm64/kernel/setup.c

@@ -57,6 +57,12 @@
 #include <asm/haoc/iee-si.h>
 #endif
 
+#ifdef CONFIG_ARCH_PHYTIUM
+#include <asm/phytium_cputype.h>
+enum phyt_soc_type phyt_soc_type_t;
+EXPORT_SYMBOL(phyt_soc_type_t);
+#endif
+
 static int num_standard_resources;
 static struct resource *standard_resources;
 
@@ -349,6 +355,9 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
 			   FW_BUG "Booted with MMU enabled!");
 	}
 
+#ifdef CONFIG_ARCH_PHYTIUM
+	phyt_soc_type_init();
+#endif
 	arm64_memblock_init();
 
 	paging_init();