update codegen and test

[n0thingNoob]

update codegen for #300

The corresponded IR and ASM:
%139 = "neura.data_mov"(%134) {dfg_id = 179 : i32, mapping_locs = [{id = 168 : i32, index_per_ii = 11 : i32, invalid_iterations = 0 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 11 : i32}, {id = 161 : i32, index_per_ii = 12 : i32, invalid_iterations = 0 : i32, per_tile_register_id = 1 : i32, resource = "register", time_step = 12 : i32}, {id = 160 : i32, index_per_ii = 13 : i32, invalid_iterations = 0 : i32, per_tile_register_id = 0 : i32, resource = "register", time_step = 13 : i32}, {id = 14 : i32, index_per_ii = 14 : i32, invalid_iterations = 0 : i32, resource = "link", time_step = 14 : i32}, {id = 200 : i32, index_per_ii = 15 : i32, invalid_iterations = 0 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 15 : i32}, {id = 200 : i32, index_per_ii = 16 : i32, invalid_iterations = 0 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 16 : i32}, {id = 200 : i32, index_per_ii = 0 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 17 : i32}, {id = 200 : i32, index_per_ii = 1 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 18 : i32}, {id = 200 : i32, index_per_ii = 2 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 19 : i32}, {id = 200 : i32, index_per_ii = 3 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 20 : i32}, {id = 200 : i32, index_per_ii = 4 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 21 : i32}, {id = 200 : i32, index_per_ii = 5 : i32, invalid_iterations = 1 : i32, per_tile_register_id = 8 : i32, resource = "register", time_step = 22 : i32}]} : (!neura.data<i1, i1>) -> !neura.data<i1, i1>

[Copilot]

Pull request overview

This PR updates Neura code generation to better handle register-transfer chains around link routing (addressing the register allocation collision described in #300), and updates/extends end-to-end MLIR FileCheck expectations accordingly.

Changes:

• Emit synthetic register-to-register transfer instructions (and include them in routing) to preserve value flow across multiple pre-/post-link register steps.
• Improve consumer rewiring to select an appropriate register based on consumer placement time instead of always wiring to the “last” register.
• Update e2e tests’ expected instruction IDs; add new GEMM checks for chained YAML/ASM and DFG output.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
lib/NeuraDialect/Transforms/GenerateCodePass.cpp	Adds synthetic register-transfer chain emission, updates consumer rewiring, and updates DFG hop-rewrite logic to model chains.
test/e2e/spmv/spmv_kernel.mlir	Updates FileCheck expectations for shifted synthetic instruction IDs.
test/e2e/gemv/gemv_kernel.mlir	Updates FileCheck expectations for shifted synthetic instruction IDs; removes trailing blank lines.
test/e2e/gemm/gemm_kernel.mlir	Adds new chain-focused checks for YAML/ASM and DFG output to validate the new routing chain behavior.
test/e2e/fir/fir_kernel.mlir	Updates FileCheck expectations for shifted synthetic instruction IDs.

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