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Arm32 thumb2 (Cortex-M) support #13815

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eab420b
initial arm32 thumb2 skeleton
cpetig Jul 4, 2026
d705a58
fix warnings
cpetig Jul 4, 2026
82b91b6
clippy fix
cpetig Jul 4, 2026
97d10f3
return instruction
cpetig Jul 4, 2026
1f2ceba
function epilog
cpetig Jul 4, 2026
f0b4e42
working first filetest
cpetig Jul 4, 2026
e10ff79
plus test
cpetig Jul 4, 2026
357466c
simplify and fix warnings
cpetig Jul 5, 2026
8cd5c56
simplification
cpetig Jul 5, 2026
f680c52
simplify
cpetig Jul 5, 2026
d892a09
more simplification
cpetig Jul 5, 2026
71cd8b5
avoid glob imports
cpetig Jul 5, 2026
0ece411
reduce imports
cpetig Jul 5, 2026
a131ab8
fix imports
cpetig Jul 5, 2026
b2818af
cut down the number of glob re-exports
cpetig Jul 5, 2026
c69977e
this is necessary to compile the most simple runtest
cpetig Jul 5, 2026
edc576e
standardize on arm32
cpetig Jul 5, 2026
072f983
undo the warning fix for pulley
cpetig Jul 5, 2026
7f6714a
clippy fix
cpetig Jul 5, 2026
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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -391,7 +391,7 @@ log = { version = "0.4.28", default-features = false }
clap = { version = "4.5.48", default-features = false, features = ["std", "derive"] }
clap_complete = "4.5.58"
hashbrown = { version = "0.17", default-features = false }
capstone = { version = "0.14.0", default-features = false, features = ['full', 'arch_x86', 'arch_riscv', 'arch_arm64', 'arch_sysz'] }
capstone = { version = "0.14.0", default-features = false, features = ['full', 'arch_x86', 'arch_riscv', 'arch_arm64', 'arch_sysz', 'arch_arm'] }
smallvec = { version = "1.15.1", features = ["union"] }
tracing = { version = "0.1.41", default-features = false }
bitflags = "2.9.4"
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3 changes: 2 additions & 1 deletion cranelift/codegen/Cargo.toml
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Expand Up @@ -93,6 +93,7 @@ unwind = ["gimli"]
# If no ISA targets are explicitly enabled, the ISA target for the host machine is enabled.
x86 = []
arm64 = []
arm32 = []
s390x = []
riscv64 = []
pulley = [
Expand All @@ -109,7 +110,7 @@ all-arch = ["all-native-arch", "pulley"]

# Option to enable all architectures that correspond to an actual native target
# (that is, exclude Pulley).
all-native-arch = ["x86", "arm64", "s390x", "riscv64"]
all-native-arch = ["x86", "arm64", "s390x", "riscv64", "arm32"]

# For dependent crates that want to serialize some parts of cranelift
enable-serde = [
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11 changes: 11 additions & 0 deletions cranelift/codegen/meta/src/isa/arm32.rs
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@@ -0,0 +1,11 @@
use crate::cdsl::isa::TargetIsa;
use crate::cdsl::settings::SettingGroupBuilder;

pub(crate) fn define() -> TargetIsa {
let settings = SettingGroupBuilder::new("arm32");

// ARM32-specific settings can be added here in the future.
// For now, we start with an empty settings group.

@bjorn3 bjorn3 Jul 4, 2026

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cg_clif would at the very least need the thumb2 (use thumb2 rather than the original thumb) and thumb-mode (actually use thumb rather than arm instructions) settings to match LLVM. And the current backend you wrote should error when either is not set.

@cpetig cpetig Jul 5, 2026

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I agree about the erroring part, do you have specific names for the flags in mind so that they are more easily compatible with cg_clif?

@cpetig cpetig Jul 5, 2026 •
edited
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I guess other settings are has_fp32, has_fp64, has_dsp, has_cbz, has_it, hwfloat_abi.

@cpetig cpetig Jul 5, 2026

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I think you mean these subtarget flags: https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/ARM/ARMSubtarget.h and https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/TargetParser/Triple.h - but at least thumb vs arm is selected by the target triple.

@bjorn3 bjorn3 Jul 6, 2026

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You can select between thumb and arm on a per-function basis in LLVM and Rust, so changing the target triple is not the only way of choosing thumb mode. #[instruction_set(arm::t32)] lowers to what is effectively #[target_feature(enable = "thumb-mode")] in the LLVM backend of rustc. And a couple of rustc targets also use target_features: "+thumb-mode" in the target spec.


TargetIsa::new("arm32", settings.build())
}
6 changes: 6 additions & 0 deletions cranelift/codegen/meta/src/isa/mod.rs
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Expand Up @@ -2,6 +2,7 @@
use crate::cdsl::isa::TargetIsa;
use std::fmt;

mod arm32;
mod arm64;
mod pulley;
mod riscv64;
Expand All @@ -13,6 +14,7 @@ pub(crate) mod x86;
pub enum Isa {
X86,
Arm64,
Arm32,
S390x,
Riscv64,
Pulley32,
Expand All @@ -31,6 +33,7 @@ impl Isa {
/// Creates isa target from arch.
pub fn from_arch(arch: &str) -> Option<Self> {
match arch {
"arm" => Some(Isa::Arm32),
"aarch64" => Some(Isa::Arm64),
"s390x" => Some(Isa::S390x),
x if ["x86_64", "i386", "i586", "i686"].contains(&x) => Some(Isa::X86),
Expand All @@ -46,6 +49,7 @@ impl Isa {
&[
Isa::X86,
Isa::Arm64,
Isa::Arm32,
Isa::S390x,
Isa::Riscv64,
Isa::Pulley32,
Expand All @@ -60,6 +64,7 @@ impl fmt::Display for Isa {
match *self {
Isa::X86 => write!(f, "x86"),
Isa::Arm64 => write!(f, "arm64"),
Isa::Arm32 => write!(f, "arm32"),
Isa::S390x => write!(f, "s390x"),
Isa::Riscv64 => write!(f, "riscv64"),
Isa::Pulley32 => write!(f, "pulley32"),
Expand All @@ -73,6 +78,7 @@ pub(crate) fn define(isas: &[Isa]) -> Vec<TargetIsa> {
.map(|isa| match isa {
Isa::X86 => x86::define(),
Isa::Arm64 => arm64::define(),
Isa::Arm32 => arm32::define(),
Isa::S390x => s390x::define(),
Isa::Riscv64 => riscv64::define(),
Isa::Pulley32 | Isa::Pulley64 => pulley::define(),
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16 changes: 16 additions & 0 deletions cranelift/codegen/meta/src/isle.rs
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Expand Up @@ -137,6 +137,7 @@ pub fn get_isle_compilations(
// Directories for lowering backends.
let src_isa_x64 = codegen_crate_dir.join("src").join("isa").join("x64");
let src_isa_aarch64 = codegen_crate_dir.join("src").join("isa").join("aarch64");
let src_isa_arm32 = codegen_crate_dir.join("src").join("isa").join("arm32");
let src_isa_s390x = codegen_crate_dir.join("src").join("isa").join("s390x");
let src_isa_risc_v = codegen_crate_dir.join("src").join("isa").join("riscv64");
#[cfg(feature = "pulley")]
Expand Down Expand Up @@ -229,6 +230,21 @@ pub fn get_isle_compilations(
.concat(),
untracked_inputs: vec![numerics_isle.clone(), clif_lower_isle.clone()],
},
// The ARM32 instruction selector.
IsleCompilation {
name: "arm32".to_string(),
output: gen_dir.join("isle_arm32.rs"),
tracked_inputs: [
vec![prelude_isle.clone(), prelude_lower_isle.clone()],
spec_inputs(&[]),
vec![
src_isa_arm32.join("inst.isle"),
src_isa_arm32.join("lower.isle"),
],
]
.concat(),
untracked_inputs: vec![numerics_isle.clone(), clif_lower_isle.clone()],
},
// The s390x instruction selector.
IsleCompilation {
name: "s390x".to_string(),
Expand Down
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