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perf(aarch64): use lr-only linkage frames for simple regular calls #13055

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36205f4
perf(aarch64): use lr-only linkage frames for simple regular calls
pnodet Apr 11, 2026
f846f2e
test(aarch64): update filetests for lr-only linkage frame mode
pnodet Apr 11, 2026
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129 changes: 92 additions & 37 deletions cranelift/codegen/src/isa/aarch64/abi.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -578,6 +578,13 @@ impl ABIMachineSpec for AArch64MachineDeps {
frame_layout: &FrameLayout,
) -> SmallInstVec<Inst> {
let setup_frame = frame_layout.setup_area_size > 0;
let lr_only_setup = setup_frame
&& AArch64MachineDeps::use_lr_only_linkage_frame(
call_conv,
flags,
isa_flags,
frame_layout,
);
let mut insts = SmallVec::new();

match Self::select_api_key(isa_flags, call_conv, setup_frame) {
Expand Down Expand Up @@ -610,64 +617,93 @@ impl ABIMachineSpec for AArch64MachineDeps {
}

if setup_frame {
// stp fp (x29), lr (x30), [sp, #-16]!
insts.push(Inst::StoreP64 {
rt: fp_reg(),
rt2: link_reg(),
mem: PairAMode::SPPreIndexed {
simm7: SImm7Scaled::maybe_from_i64(-16, types::I64).unwrap(),
},
flags: MemFlags::trusted(),
});
if lr_only_setup {
// str lr (x30), [sp, #-16]!
insts.push(Inst::Store64 {
rd: link_reg(),
mem: AMode::SPPreIndexed {
simm9: SImm9::maybe_from_i64(-16).unwrap(),
},
flags: MemFlags::trusted(),
});
} else {
// stp fp (x29), lr (x30), [sp, #-16]!
insts.push(Inst::StoreP64 {
rt: fp_reg(),
rt2: link_reg(),
mem: PairAMode::SPPreIndexed {
simm7: SImm7Scaled::maybe_from_i64(-16, types::I64).unwrap(),
},
flags: MemFlags::trusted(),
});

if flags.unwind_info() {
insts.push(Inst::Unwind {
inst: UnwindInst::PushFrameRegs {
offset_upward_to_caller_sp: frame_layout.setup_area_size,
if flags.unwind_info() {
insts.push(Inst::Unwind {
inst: UnwindInst::PushFrameRegs {
offset_upward_to_caller_sp: frame_layout.setup_area_size,
},
});
}

// mov fp (x29), sp. This uses the ADDI rd, rs, 0 form of `MOV` because
// the usual encoding (`ORR`) does not work with SP.
insts.push(Inst::AluRRImm12 {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_fp_reg(),
rn: stack_reg(),
imm12: Imm12 {
bits: 0,
shift12: false,
},
});
}

// mov fp (x29), sp. This uses the ADDI rd, rs, 0 form of `MOV` because
// the usual encoding (`ORR`) does not work with SP.
insts.push(Inst::AluRRImm12 {
alu_op: ALUOp::Add,
size: OperandSize::Size64,
rd: writable_fp_reg(),
rn: stack_reg(),
imm12: Imm12 {
bits: 0,
shift12: false,
},
});
}

insts
}

fn gen_epilogue_frame_restore(
call_conv: isa::CallConv,
_flags: &settings::Flags,
_isa_flags: &aarch64_settings::Flags,
flags: &settings::Flags,
isa_flags: &aarch64_settings::Flags,
frame_layout: &FrameLayout,
) -> SmallInstVec<Inst> {
let setup_frame = frame_layout.setup_area_size > 0;
let lr_only_setup = setup_frame
&& AArch64MachineDeps::use_lr_only_linkage_frame(
call_conv,
flags,
isa_flags,
frame_layout,
);
let mut insts = SmallVec::new();

if setup_frame {
// N.B.: sp is already adjusted to the appropriate place by the
// clobber-restore code (which also frees the fixed frame). Hence, there
// is no need for the usual `mov sp, fp` here.

// `ldp fp, lr, [sp], #16`
insts.push(Inst::LoadP64 {
rt: writable_fp_reg(),
rt2: writable_link_reg(),
mem: PairAMode::SPPostIndexed {
simm7: SImm7Scaled::maybe_from_i64(16, types::I64).unwrap(),
},
flags: MemFlags::trusted(),
});
if lr_only_setup {
// `ldr lr, [sp], #16`
insts.push(Inst::ULoad64 {
rd: writable_link_reg(),
mem: AMode::SPPostIndexed {
simm9: SImm9::maybe_from_i64(16).unwrap(),
},
flags: MemFlags::trusted(),
});
} else {
// `ldp fp, lr, [sp], #16`
insts.push(Inst::LoadP64 {
rt: writable_fp_reg(),
rt2: writable_link_reg(),
mem: PairAMode::SPPostIndexed {
simm7: SImm7Scaled::maybe_from_i64(16, types::I64).unwrap(),
},
flags: MemFlags::trusted(),
});
}
}

if call_conv == isa::CallConv::Tail && frame_layout.tail_args_size > 0 {
Expand Down Expand Up @@ -1248,6 +1284,25 @@ impl ABIMachineSpec for AArch64MachineDeps {
}

impl AArch64MachineDeps {
fn use_lr_only_linkage_frame(
call_conv: isa::CallConv,
flags: &settings::Flags,
isa_flags: &aarch64_settings::Flags,
frame_layout: &FrameLayout,
) -> bool {
call_conv != isa::CallConv::Tail
&& frame_layout.function_calls == FunctionCalls::Regular
&& frame_layout.setup_area_size == 16
&& !flags.preserve_frame_pointers()
&& !flags.unwind_info()
&& !isa_flags.sign_return_address()
&& frame_layout.incoming_args_size == 0
&& frame_layout.tail_args_size == frame_layout.incoming_args_size
&& frame_layout.clobber_size == 0
&& frame_layout.fixed_frame_storage_size == 0
&& frame_layout.outgoing_args_size == 0
}

fn gen_probestack_unroll(insts: &mut SmallInstVec<Inst>, guard_size: u32, probe_count: u32) {
// When manually unrolling adjust the stack pointer and then write a zero
// to the stack at that offset. This generates something like
Expand Down
16 changes: 7 additions & 9 deletions cranelift/filetests/filetests/isa/aarch64/bti.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -149,25 +149,23 @@ block0(v0: i64):

; VCode:
; bti c
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str lr, [sp, #-16]!
; block0:
; load_ext_name_far x3, TestCase(%g)+0
; blr x3
; ldp fp, lr, [sp], #16
; ldr lr, [sp], #16
; ret
;
; Disassembled:
; block0: ; offset 0x0
; hint #0x22
; stp x29, x30, [sp, #-0x10]!
; mov x29, sp
; block1: ; offset 0xc
; ldr x3, #0x14
; b #0x1c
; str x30, [sp, #-0x10]!
; block1: ; offset 0x8
; ldr x3, #0x10
; b #0x18
; .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
; .byte 0x00, 0x00, 0x00, 0x00
; blr x3
; ldp x29, x30, [sp], #0x10
; ldr x30, [sp], #0x10
; ret

17 changes: 8 additions & 9 deletions cranelift/filetests/filetests/isa/aarch64/bti_with_csdb.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -151,24 +151,23 @@ block0(v0: i64):

; VCode:
; bti c
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str lr, [sp, #-16]!
; block0:
; load_ext_name_far x3, TestCase(%g)+0
; blr x3
; ldp fp, lr, [sp], #16
; ldr lr, [sp], #16
; ret
;
; Disassembled:
; block0: ; offset 0x0
; hint #0x22
; stp x29, x30, [sp, #-0x10]!
; mov x29, sp
; block1: ; offset 0xc
; ldr x3, #0x14
; b #0x1c
; str x30, [sp, #-0x10]!
; block1: ; offset 0x8
; ldr x3, #0x10
; b #0x18
; .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
; .byte 0x00, 0x00, 0x00, 0x00
; blr x3
; ldp x29, x30, [sp], #0x10
; ldr x30, [sp], #0x10
; ret

12 changes: 5 additions & 7 deletions cranelift/filetests/filetests/isa/aarch64/call-indirect.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,17 @@ block0(v0: i64, v1: i64):
}

; VCode:
; stp fp, lr, [sp, #-16]!
; mov fp, sp
; str lr, [sp, #-16]!
; block0:
; blr x1
; ldp fp, lr, [sp], #16
; ldr lr, [sp], #16
; ret
;
; Disassembled:
; block0: ; offset 0x0
; stp x29, x30, [sp, #-0x10]!
; mov x29, sp
; block1: ; offset 0x8
; str x30, [sp, #-0x10]!
; block1: ; offset 0x4
; blr x1
; ldp x29, x30, [sp], #0x10
; ldr x30, [sp], #0x10
; ret

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