Correct 2 s390x Vector Evaluate bugs

cranelift/codegen/src/isa/s390x/lower.isle

@@ -721,14 +721,14 @@
                                (trap_code_integer_overflow))))
 (rule 1 (maybe_trap_if_sdiv_overflow true $I128 $I128 x y)
       (let (
-            ;; We need to trap when y == INT_MIN && x == -1
-            ;; y == INT_MIN is implemented as y == -y, as -INT_MIN == INT_MIN.
-            ;; This checks that y == -y, by using Not-Xor for bitwise
-            ;; equality, producing all 0b1's (-1u128) when y == -y.
-            ;; Then it uses band to include the x == -1 check as well.
-            ;; using (band x (bnot (bxor y neg_division))) variant of vec eval
-            (neg_divisor Reg (vec_neg $I128 y))
-            (reg Reg (vec_eval $I128 0b00001001 x y neg_divisor))
+            ;; We need to trap when x == INT_MIN && y == -1
+            ;; y == INT_MIN is implemented as x == -x, as -INT_MIN == INT_MIN.
+            ;; This checks that x == -x, by using Not-Xor for bitwise
+            ;; equality, producing all 0b1's (-1u128) when x == -x.
+            ;; Then it uses band to include the y == -1 check as well.
+            ;; using (band y (bnot (bxor x neg_division))) variant of vec eval
+            (neg_dividend Reg (vec_neg $I128 x))
+            (reg Reg (vec_eval $I128 0b00001001 y x neg_dividend))
             ;; finally, we check that the combination of x & y == -y is -1
             (flags ProducesFlags (vec_elt_icmps reg (vec_imm $I128 -1))))
         (trap_if flags
@@ -1167,9 +1167,9 @@
 (rule 17 (lower (has_type (and (vxrs_ext3_enabled) (vr128_ty ty)) (band _ x (band _ y (bnot _ z)))))
       (vec_eval ty 0b00000010 x y z))
 (rule 18 (lower (has_type (and (vxrs_ext3_enabled) (vr128_ty ty)) (band _ (band _ x (bnot _ y)) z)))
-      (vec_eval ty 0b00000100 y x z))
+      (vec_eval ty 0b00000100 x y z))
 (rule 19 (lower (has_type (and (vxrs_ext3_enabled) (vr128_ty ty)) (band _ x (band _ (bnot _ y) z))))
-      (vec_eval ty 0b00000100 z x y))
+      (vec_eval ty 0b00000100 x y z))
 
 ;; Not-and three vector registers
 (rule 20 (lower (has_type (and (vxrs_ext3_enabled) (vr128_ty ty)) (bnot _ (band _ (band _ x y) z))))

cranelift/filetests/filetests/isa/s390x/arithmetic-arch15.clif

@@ -86,8 +86,8 @@ block0(v0: i128, v1: i128):
 ; block0:
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
-;   vlcq %v6, %v3
-;   veval %v16, %v1, %v3, %v6, 9
+;   vlcq %v6, %v1
+;   veval %v16, %v3, %v1, %v6, 9
 ;   vrepib %v17, 255
 ;   vecq %v16, %v17
 ;   jge .+2 # trap=int_ovf
@@ -99,9 +99,9 @@ block0(v0: i128, v1: i128):
 ; block0: ; offset 0x0
 ;   vl %v1, 0(%r3)
 ;   vl %v3, 0(%r4)
-;   vlc %v6, %v3, 4
-;   .byte 0xe7, 0x01
-;   lper %f0, %f9
+;   vlc %v6, %v1, 4
+;   .byte 0xe7, 0x03
+;   lpr %r0, %r9
 ;   ld %f8, 0x710(%r8, %r14)
 ;   .byte 0x00, 0xff
 ;   .byte 0x08, 0x45

cranelift/filetests/filetests/isa/s390x/vec-bitwise-arch15.clif

@@ -67,14 +67,14 @@ block0(v0: i64x2, v1: i64x2, v2: i64x2):
 
 ; VCode:
 ; block0:
-;   veval %v24, %v25, %v24, %v26, 4
+;   veval %v24, %v24, %v25, %v26, 4
 ;   br %r14
 ;
 ; Disassembled:
 ; block0: ; offset 0x0
-;   .byte 0xe7, 0x89
-;   .byte 0x80, 0x04
-;   mc 0x7fe, 0x88
+;   .byte 0xe7, 0x88
+;   stm %r0, %r4, 0xf88(%r10)
+;   br %r14
 
 function %band_band_notc_i64x2(i64x2, i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2, v2: i64x2):